SPRSP68B January   2023  – November 2023 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
        1. 5.4.1.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption - VREG Enable - Internal Supply
      2. 6.5.2 System Current Consumption - VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Current Consumption Graphs
      5. 6.5.5 Reducing Current Consumption
        1. 6.5.5.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for PN Package
    8. 6.8  Thermal Resistance Characteristics for PM Package
    9. 6.9  Thermal Resistance Characteristics for PHP Package
    10. 6.10 Thermal Resistance Characteristics for RHB Package
    11. 6.11 Thermal Design Considerations
    12. 6.12 Thermal Design Considerations for AEC-Q100 Grade 0
      1. 6.12.1 Simple Frequency Reduction
      2. 6.12.2 Dynamic Frequency Reduction
      3. 6.12.3 Flash Considerations
    13. 6.13 System
      1. 6.13.1  Power Management Module (PMM)
        1. 6.13.1.1 Introduction
        2. 6.13.1.2 Overview
          1. 6.13.1.2.1 Power Rail Monitors
            1. 6.13.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.13.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.13.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.13.1.2.2 External Supervisor Usage
          3. 6.13.1.2.3 Delay Blocks
          4. 6.13.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.13.1.2.5 VREGENZ
        3. 6.13.1.3 External Components
          1. 6.13.1.3.1 Decoupling Capacitors
            1. 6.13.1.3.1.1 VDDIO Decoupling
            2. 6.13.1.3.1.2 VDD Decoupling
        4. 6.13.1.4 Power Sequencing
          1. 6.13.1.4.1 Supply Pins Ganging
          2. 6.13.1.4.2 Signal Pins Power Sequence
          3. 6.13.1.4.3 Supply Pins Power Sequence
            1. 6.13.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.13.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.13.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.13.1.4.3.4 Supply Slew Rate
        5. 6.13.1.5 Recommended Operating Conditions Applicability to the PMM
        6. 6.13.1.6 Power Management Module Electrical Data and Timing
          1. 6.13.1.6.1 Power Management Module Operating Conditions
          2. 6.13.1.6.2 Power Management Module Characteristics
      2. 6.13.2  Reset Timing
        1. 6.13.2.1 Reset Sources
        2. 6.13.2.2 Reset Electrical Data and Timing
          1. 6.13.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.13.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.13.2.2.3 Reset Timing Diagrams
      3. 6.13.3  Clock Specifications
        1. 6.13.3.1 Clock Sources
        2. 6.13.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.13.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.13.3.2.1.1 Input Clock Frequency
            2. 6.13.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.13.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.13.3.2.1.4 X1 Timing Requirements
            5. 6.13.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.13.3.2.1.6 APLL Characteristics
            7. 6.13.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.13.3.2.1.8 Internal Clock Frequencies
        3. 6.13.3.3 Input Clocks and PLLs
        4. 6.13.3.4 XTAL Oscillator
          1. 6.13.3.4.1 Introduction
          2. 6.13.3.4.2 Overview
            1. 6.13.3.4.2.1 Electrical Oscillator
              1. 6.13.3.4.2.1.1 Modes of Operation
                1. 6.13.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.13.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.13.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.13.3.4.2.2 Quartz Crystal
            3. 6.13.3.4.2.3 GPIO Modes of Operation
          3. 6.13.3.4.3 Functional Operation
            1. 6.13.3.4.3.1 ESR – Effective Series Resistance
            2. 6.13.3.4.3.2 Rneg – Negative Resistance
            3. 6.13.3.4.3.3 Start-up Time
              1. 6.13.3.4.3.3.1 X1/X2 Precondition
            4. 6.13.3.4.3.4 DL – Drive Level
          4. 6.13.3.4.4 How to Choose a Crystal
          5. 6.13.3.4.5 Testing
          6. 6.13.3.4.6 Common Problems and Debug Tips
          7. 6.13.3.4.7 Crystal Oscillator Specifications
            1. 6.13.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.13.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.13.3.4.7.3 Crystal Oscillator Parameters
            4. 6.13.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 6.13.3.5 Internal Oscillators
          1. 6.13.3.5.1 INTOSC Characteristics
          2. 6.13.3.5.2 INTOSC2 with External Precision Resistor – ExtR
      4. 6.13.4  Flash Parameters
        1. 6.13.4.1 Flash Parameters 
      5. 6.13.5  RAM Specifications
      6. 6.13.6  ROM Specifications
      7. 6.13.7  Emulation/JTAG
        1. 6.13.7.1 JTAG Electrical Data and Timing
          1. 6.13.7.1.1 JTAG Timing Requirements
          2. 6.13.7.1.2 JTAG Switching Characteristics
          3. 6.13.7.1.3 JTAG Timing Diagram
        2. 6.13.7.2 cJTAG Electrical Data and Timing
          1. 6.13.7.2.1 cJTAG Timing Requirements
          2. 6.13.7.2.2 cJTAG Switching Characteristics
          3. 6.13.7.2.3 cJTAG Timing Diagram
      8. 6.13.8  GPIO Electrical Data and Timing
        1. 6.13.8.1 GPIO – Output Timing
          1. 6.13.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.13.8.1.2 General-Purpose Output Timing Diagram
        2. 6.13.8.2 GPIO – Input Timing
          1. 6.13.8.2.1 General-Purpose Input Timing Requirements
          2. 6.13.8.2.2 Sampling Mode
        3. 6.13.8.3 Sampling Window Width for Input Signals
      9. 6.13.9  Interrupts
        1. 6.13.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.13.9.1.1 External Interrupt Timing Requirements
          2. 6.13.9.1.2 External Interrupt Switching Characteristics
          3. 6.13.9.1.3 External Interrupt Timing
      10. 6.13.10 Low-Power Modes
        1. 6.13.10.1 Clock-Gating Low-Power Modes
        2. 6.13.10.2 Low-Power Mode Wake-up Timing
          1. 6.13.10.2.1 IDLE Mode Timing Requirements
          2. 6.13.10.2.2 IDLE Mode Switching Characteristics
          3. 6.13.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.13.10.2.4 STANDBY Mode Timing Requirements
          5. 6.13.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.13.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.13.10.2.7 HALT Mode Timing Requirements
          8. 6.13.10.2.8 HALT Mode Switching Characteristics
          9. 6.13.10.2.9 HALT Entry and Exit Timing Diagram
    14. 6.14 Analog Peripherals
      1. 6.14.1 Analog Pins and Internal Connections
      2. 6.14.2 Analog Signal Descriptions
      3. 6.14.3 Analog-to-Digital Converter (ADC)
        1. 6.14.3.1 ADC Configurability
          1. 6.14.3.1.1 Signal Mode
        2. 6.14.3.2 ADC Electrical Data and Timing
          1. 6.14.3.2.1 ADC Operating Conditions
          2. 6.14.3.2.2 ADC Characteristics
          3. 6.14.3.2.3 ADC Performance Per Pin
          4. 6.14.3.2.4 ADC Input Model
          5. 6.14.3.2.5 ADC Timing Diagrams
      4. 6.14.4 Temperature Sensor
        1. 6.14.4.1 Temperature Sensor Electrical Data and Timing
          1. 6.14.4.1.1 Temperature Sensor Characteristics
      5. 6.14.5 Comparator Subsystem (CMPSS)
        1. 6.14.5.1 CMPSS Module Variants
        2. 6.14.5.2 CMPx_DACL
        3. 6.14.5.3 CMPSS Connectivity Diagram
        4. 6.14.5.4 Block Diagrams
        5. 6.14.5.5 CMPSS Electrical Data and Timing
          1. 6.14.5.5.1 CMPSS Comparator Electrical Characteristics
          2. 6.14.5.5.2 CMPSS_LITE Comparator Electrical Characteristics
          3.        CMPSS Comparator Input Referred Offset and Hysteresis
          4. 6.14.5.5.3 CMPSS DAC Static Electrical Characteristics
          5. 6.14.5.5.4 CMPSS_LITE DAC Static Electrical Characteristics
          6. 6.14.5.5.5 CMPSS Illustrative Graphs
          7. 6.14.5.5.6 CMPSS DAC Dynamic Error
          8. 6.14.5.5.7 Buffered Output from CMPx_DACL Operating Conditions
          9. 6.14.5.5.8 Buffered Output from CMPx_DACL Electrical Characteristics
    15. 6.15 Control Peripherals
      1. 6.15.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.15.1.1 Control Peripherals Synchronization
        2. 6.15.1.2 ePWM Electrical Data and Timing
          1. 6.15.1.2.1 ePWM Timing Requirements
          2. 6.15.1.2.2 ePWM Switching Characteristics
          3. 6.15.1.2.3 Trip-Zone Input Timing
            1. 6.15.1.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.15.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.15.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.15.2.1 HRPWM Electrical Data and Timing
          1. 6.15.2.1.1 High-Resolution PWM Characteristics
      3. 6.15.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.15.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.15.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.15.4 Enhanced Capture (eCAP)
        1. 6.15.4.1 eCAP Block Diagram
        2. 6.15.4.2 eCAP Synchronization
        3. 6.15.4.3 eCAP Electrical Data and Timing
          1. 6.15.4.3.1 eCAP Timing Requirements
          2. 6.15.4.3.2 eCAP Switching Characteristics
      5. 6.15.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.15.5.1 eQEP Electrical Data and Timing
          1. 6.15.5.1.1 eQEP Timing Requirements
          2. 6.15.5.1.2 eQEP Switching Characteristics
    16. 6.16 Communications Peripherals
      1. 6.16.1 Controller Area Network (CAN)
      2. 6.16.2 Modular Controller Area Network (MCAN)
      3. 6.16.3 Inter-Integrated Circuit (I2C)
        1. 6.16.3.1 I2C Electrical Data and Timing
          1. 6.16.3.1.1 I2C Timing Requirements
          2. 6.16.3.1.2 I2C Switching Characteristics
          3. 6.16.3.1.3 I2C Timing Diagram
      4. 6.16.4 Power Management Bus (PMBus) Interface
        1. 6.16.4.1 PMBus Electrical Data and Timing
          1. 6.16.4.1.1 PMBus Electrical Characteristics
          2. 6.16.4.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.16.4.1.3 PMBus Standard Mode Switching Characteristics
      5. 6.16.5 Serial Communications Interface (SCI)
      6. 6.16.6 Serial Peripheral Interface (SPI)
        1. 6.16.6.1 SPI Master Mode Timings
          1. 6.16.6.1.1 SPI Master Mode Timing Requirements
          2. 6.16.6.1.2 SPI Master Mode Switching Characteristics - Clock Phase 0
          3. 6.16.6.1.3 SPI Master Mode Switching Characteristics - Clock Phase 1
          4. 6.16.6.1.4 SPI Master Mode Timing Diagrams
        2. 6.16.6.2 SPI Slave Mode Timings
          1. 6.16.6.2.1 SPI Slave Mode Timing Requirements
          2. 6.16.6.2.2 SPI Slave Mode Switching Characteristics
          3. 6.16.6.2.3 SPI Slave Mode Timing Diagrams
      7. 6.16.7 Local Interconnect Network (LIN)
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
      2. 7.3.2 Flash Memory Map
      3. 7.3.3 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  C28x Processor
      1. 7.5.1 Floating-Point Unit (FPU)
      2. 7.5.2 Trigonometric Math Unit (TMU)
      3. 7.5.3 VCRC Unit
      4. 7.5.4 Lockstep Compare Module (LCM)
    6. 7.6  Device Boot Modes
      1. 7.6.1 Device Boot Configurations
        1. 7.6.1.1 Configuring Boot Mode Pins
        2. 7.6.1.2 Configuring Boot Mode Table Options
      2. 7.6.2 GPIO Assignments
    7. 7.7  Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8  Watchdog
    9. 7.9  C28x Timers
    10. 7.10 Dual-Clock Comparator (DCC)
      1. 7.10.1 Features
      2. 7.10.2 Mapping of DCCx Clock Source Inputs
    11. 7.11 Functional Safety
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 On-Board Charger (OBC)
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 OBC Resources
        2. 8.3.1.2 Automotive Pump
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Automotive Pump Resources
        3. 8.3.1.3 Positive Temperature Coefficient (PTC) Heater
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 PTC Resources
        4. 8.3.1.4 Automotive HVAC Compressor
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 Automotive HVAC Compressor Resources
        5. 8.3.1.5 Single-Phase Line-Interactive Uninterruptable Power Supply (UPS)
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 Single-Phase Line-Interactive UPS Resources
        6. 8.3.1.6 AC Drive Power Stage Module
          1. 8.3.1.6.1 System Block Diagram
          2. 8.3.1.6.2 AC Drive Power Stage Module Resources
        7. 8.3.1.7 Server or Telecom Power Supply Unit (PSU)
          1. 8.3.1.7.1 System Block Diagram
          2. 8.3.1.7.2 Server or Telecom PSU Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
  • PHP|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.2 GPIO Assignments

This section details the GPIOs and boot option values used for boot mode set in the BOOT_DEF memory location located at Z1-OTP-BOOTDEF-LOW/ Z2-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH/ Z2-OTP-BOOTDEF-HIGH. Refer to Configuring Boot Mode Table Options on how to configure BOOT_DEF. When selecting a boot mode option, make sure to verify that the necessary pins are available in the pin mux options for the specific device package being used.

Table 7-11 SCI Boot Options
OPTIONBOOTDEF VALUESCITXDA GPIOSCIRXDA GPIO
0 (default)0x01GPIO29GPIO28
10x21GPIO1GPIO0
20x41GPIO8GPIO9
30x61GPIO7GPIO3
40x81GPIO16GPIO3
Table 7-12 CAN Boot Options
OPTIONBOOTDEF VALUECANTXA GPIOCANRXA GPIO
0 (default)0x02GPIO7GPIO5
10x22GPIO32GPIO33
20x42GPIO2GPIO3
3 0x62 GPIO13 GPIO12
Note: F280013x and F280015x CANTXA GPIO Option 0 (default) selections are different. All other CAN boot option GPIO selections are the same. Please refer to respective device data sheet for details.
Table 7-13 CAN FD Boot Options
OPTION BOOTDEF VALUE MCANTXA GPIO MCANRXA GPIO
0 (default) 0x08 GPIO4 GPIO5
1 0x28 GPIO1 GPIO0
2 0x48 GPIO13 GPIO12
3 (DEBUG-Send Test) 0x68 GPIO4 GPIO5
4 (DEBUG-Send Test) 0x88 GPIO1 GPIO0
5 (DEBUG-Send Test) 0xA8 GPIO13 GPIO12
Table 7-14 I2C Boot Options
OPTIONBOOTDEF VALUESDAA GPIOSCLA GPIO
00x07GPIO0GPIO1
10x27GPIO32GPIO33
20x47GPIO5GPIO4
Table 7-15 RAM Boot Options
OPTIONBOOTDEF VALUERAM ENTRY POINT
(ADDRESS)
00x050x0000 0000
Table 7-16 Flash Boot Options
OPTIONBOOTDEF VALUEFLASH ENTRY POINT
(ADDRESS)		FLASH SECTOR
0 (default)0x030x0008 0000Bank0 Sector 0
10x230x0008 8000Bank 0 Sector 32
20x430x0008 FFF0Bank 0 End of Sector 63
30x630x0009 0000Bank 0 Sector 64
4 0x83 0x0009 8000 Bank 0 Sector 96
6 0xA3 0x0009 FFF0 Bank 0 End of Sector 127
Table 7-17 Secure Flash Boot Options
OPTION BOOTDEF VALUE FLASH ENTRY POINT
(ADDRESS)		 FLASH SECTOR
0 (default) 0x0A 0x0008 0000 Bank0 Sector 0
1 0x2A 0x0008 8000 Bank 0 Sector 32
2 0x4A 0x0008 FFF0 Bank 0 End of Sector 63
3 0x6A 0x0009 0000 Bank 0 Sector 64
4 0x8A 0x0009 8000 Bank 0 Sector 96
Table 7-18 Wait Boot Options
OPTIONBOOTDEF VALUEWATCHDOG
00x04Enabled
10x24Disabled
Table 7-19 SPI Boot Options
OPTION BOOTDEF VALUE SPISIMOA SPISOMIA SPICLKA SPISTEA
0 0x06 GPIO7 GPIO1 GPIO3 GPIO5
1 0x26 GPIO16 GPIO1 GPIO3 GPIO0
2 0x46 GPIO8 GPIO10 GPIO9 GPIO11
3 0x66 GPIO16 GPIO13 GPIO12 GPIO29
Table 7-20 Parallel Boot Options
OPTIONBOOTDEF VALUED0-D7 GPIO28x(DSP) CONTROL GPIOHOST CONTROL GPIO
0 (default)0x00D0 - GPIO0GPIO224GPIO242
D1 - GPIO1
D2 - GPIO3
D3 - GPIO4
D4 - GPIO5
D5 - GPIO7
D6 - GPIO28
D7 - GPIO29
10x20D0 - GPIO0GPIO12GPIO13
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
2 0x40 D0 - GPIO0 GPIO16 GPIO29
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7