SPRSP68B January   2023  – November 2023 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
        1. 5.4.1.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption - VREG Enable - Internal Supply
      2. 6.5.2 System Current Consumption - VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Current Consumption Graphs
      5. 6.5.5 Reducing Current Consumption
        1. 6.5.5.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for PN Package
    8. 6.8  Thermal Resistance Characteristics for PM Package
    9. 6.9  Thermal Resistance Characteristics for PHP Package
    10. 6.10 Thermal Resistance Characteristics for RHB Package
    11. 6.11 Thermal Design Considerations
    12. 6.12 Thermal Design Considerations for AEC-Q100 Grade 0
      1. 6.12.1 Simple Frequency Reduction
      2. 6.12.2 Dynamic Frequency Reduction
      3. 6.12.3 Flash Considerations
    13. 6.13 System
      1. 6.13.1  Power Management Module (PMM)
        1. 6.13.1.1 Introduction
        2. 6.13.1.2 Overview
          1. 6.13.1.2.1 Power Rail Monitors
            1. 6.13.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.13.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.13.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.13.1.2.2 External Supervisor Usage
          3. 6.13.1.2.3 Delay Blocks
          4. 6.13.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.13.1.2.5 VREGENZ
        3. 6.13.1.3 External Components
          1. 6.13.1.3.1 Decoupling Capacitors
            1. 6.13.1.3.1.1 VDDIO Decoupling
            2. 6.13.1.3.1.2 VDD Decoupling
        4. 6.13.1.4 Power Sequencing
          1. 6.13.1.4.1 Supply Pins Ganging
          2. 6.13.1.4.2 Signal Pins Power Sequence
          3. 6.13.1.4.3 Supply Pins Power Sequence
            1. 6.13.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.13.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.13.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.13.1.4.3.4 Supply Slew Rate
        5. 6.13.1.5 Recommended Operating Conditions Applicability to the PMM
        6. 6.13.1.6 Power Management Module Electrical Data and Timing
          1. 6.13.1.6.1 Power Management Module Operating Conditions
          2. 6.13.1.6.2 Power Management Module Characteristics
      2. 6.13.2  Reset Timing
        1. 6.13.2.1 Reset Sources
        2. 6.13.2.2 Reset Electrical Data and Timing
          1. 6.13.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.13.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.13.2.2.3 Reset Timing Diagrams
      3. 6.13.3  Clock Specifications
        1. 6.13.3.1 Clock Sources
        2. 6.13.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.13.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.13.3.2.1.1 Input Clock Frequency
            2. 6.13.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.13.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.13.3.2.1.4 X1 Timing Requirements
            5. 6.13.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.13.3.2.1.6 APLL Characteristics
            7. 6.13.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.13.3.2.1.8 Internal Clock Frequencies
        3. 6.13.3.3 Input Clocks and PLLs
        4. 6.13.3.4 XTAL Oscillator
          1. 6.13.3.4.1 Introduction
          2. 6.13.3.4.2 Overview
            1. 6.13.3.4.2.1 Electrical Oscillator
              1. 6.13.3.4.2.1.1 Modes of Operation
                1. 6.13.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.13.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.13.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.13.3.4.2.2 Quartz Crystal
            3. 6.13.3.4.2.3 GPIO Modes of Operation
          3. 6.13.3.4.3 Functional Operation
            1. 6.13.3.4.3.1 ESR – Effective Series Resistance
            2. 6.13.3.4.3.2 Rneg – Negative Resistance
            3. 6.13.3.4.3.3 Start-up Time
              1. 6.13.3.4.3.3.1 X1/X2 Precondition
            4. 6.13.3.4.3.4 DL – Drive Level
          4. 6.13.3.4.4 How to Choose a Crystal
          5. 6.13.3.4.5 Testing
          6. 6.13.3.4.6 Common Problems and Debug Tips
          7. 6.13.3.4.7 Crystal Oscillator Specifications
            1. 6.13.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.13.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.13.3.4.7.3 Crystal Oscillator Parameters
            4. 6.13.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 6.13.3.5 Internal Oscillators
          1. 6.13.3.5.1 INTOSC Characteristics
          2. 6.13.3.5.2 INTOSC2 with External Precision Resistor – ExtR
      4. 6.13.4  Flash Parameters
        1. 6.13.4.1 Flash Parameters 
      5. 6.13.5  RAM Specifications
      6. 6.13.6  ROM Specifications
      7. 6.13.7  Emulation/JTAG
        1. 6.13.7.1 JTAG Electrical Data and Timing
          1. 6.13.7.1.1 JTAG Timing Requirements
          2. 6.13.7.1.2 JTAG Switching Characteristics
          3. 6.13.7.1.3 JTAG Timing Diagram
        2. 6.13.7.2 cJTAG Electrical Data and Timing
          1. 6.13.7.2.1 cJTAG Timing Requirements
          2. 6.13.7.2.2 cJTAG Switching Characteristics
          3. 6.13.7.2.3 cJTAG Timing Diagram
      8. 6.13.8  GPIO Electrical Data and Timing
        1. 6.13.8.1 GPIO – Output Timing
          1. 6.13.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.13.8.1.2 General-Purpose Output Timing Diagram
        2. 6.13.8.2 GPIO – Input Timing
          1. 6.13.8.2.1 General-Purpose Input Timing Requirements
          2. 6.13.8.2.2 Sampling Mode
        3. 6.13.8.3 Sampling Window Width for Input Signals
      9. 6.13.9  Interrupts
        1. 6.13.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.13.9.1.1 External Interrupt Timing Requirements
          2. 6.13.9.1.2 External Interrupt Switching Characteristics
          3. 6.13.9.1.3 External Interrupt Timing
      10. 6.13.10 Low-Power Modes
        1. 6.13.10.1 Clock-Gating Low-Power Modes
        2. 6.13.10.2 Low-Power Mode Wake-up Timing
          1. 6.13.10.2.1 IDLE Mode Timing Requirements
          2. 6.13.10.2.2 IDLE Mode Switching Characteristics
          3. 6.13.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.13.10.2.4 STANDBY Mode Timing Requirements
          5. 6.13.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.13.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.13.10.2.7 HALT Mode Timing Requirements
          8. 6.13.10.2.8 HALT Mode Switching Characteristics
          9. 6.13.10.2.9 HALT Entry and Exit Timing Diagram
    14. 6.14 Analog Peripherals
      1. 6.14.1 Analog Pins and Internal Connections
      2. 6.14.2 Analog Signal Descriptions
      3. 6.14.3 Analog-to-Digital Converter (ADC)
        1. 6.14.3.1 ADC Configurability
          1. 6.14.3.1.1 Signal Mode
        2. 6.14.3.2 ADC Electrical Data and Timing
          1. 6.14.3.2.1 ADC Operating Conditions
          2. 6.14.3.2.2 ADC Characteristics
          3. 6.14.3.2.3 ADC Performance Per Pin
          4. 6.14.3.2.4 ADC Input Model
          5. 6.14.3.2.5 ADC Timing Diagrams
      4. 6.14.4 Temperature Sensor
        1. 6.14.4.1 Temperature Sensor Electrical Data and Timing
          1. 6.14.4.1.1 Temperature Sensor Characteristics
      5. 6.14.5 Comparator Subsystem (CMPSS)
        1. 6.14.5.1 CMPSS Module Variants
        2. 6.14.5.2 CMPx_DACL
        3. 6.14.5.3 CMPSS Connectivity Diagram
        4. 6.14.5.4 Block Diagrams
        5. 6.14.5.5 CMPSS Electrical Data and Timing
          1. 6.14.5.5.1 CMPSS Comparator Electrical Characteristics
          2. 6.14.5.5.2 CMPSS_LITE Comparator Electrical Characteristics
          3.        CMPSS Comparator Input Referred Offset and Hysteresis
          4. 6.14.5.5.3 CMPSS DAC Static Electrical Characteristics
          5. 6.14.5.5.4 CMPSS_LITE DAC Static Electrical Characteristics
          6. 6.14.5.5.5 CMPSS Illustrative Graphs
          7. 6.14.5.5.6 CMPSS DAC Dynamic Error
          8. 6.14.5.5.7 Buffered Output from CMPx_DACL Operating Conditions
          9. 6.14.5.5.8 Buffered Output from CMPx_DACL Electrical Characteristics
    15. 6.15 Control Peripherals
      1. 6.15.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.15.1.1 Control Peripherals Synchronization
        2. 6.15.1.2 ePWM Electrical Data and Timing
          1. 6.15.1.2.1 ePWM Timing Requirements
          2. 6.15.1.2.2 ePWM Switching Characteristics
          3. 6.15.1.2.3 Trip-Zone Input Timing
            1. 6.15.1.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.15.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.15.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.15.2.1 HRPWM Electrical Data and Timing
          1. 6.15.2.1.1 High-Resolution PWM Characteristics
      3. 6.15.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.15.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.15.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.15.4 Enhanced Capture (eCAP)
        1. 6.15.4.1 eCAP Block Diagram
        2. 6.15.4.2 eCAP Synchronization
        3. 6.15.4.3 eCAP Electrical Data and Timing
          1. 6.15.4.3.1 eCAP Timing Requirements
          2. 6.15.4.3.2 eCAP Switching Characteristics
      5. 6.15.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.15.5.1 eQEP Electrical Data and Timing
          1. 6.15.5.1.1 eQEP Timing Requirements
          2. 6.15.5.1.2 eQEP Switching Characteristics
    16. 6.16 Communications Peripherals
      1. 6.16.1 Controller Area Network (CAN)
      2. 6.16.2 Modular Controller Area Network (MCAN)
      3. 6.16.3 Inter-Integrated Circuit (I2C)
        1. 6.16.3.1 I2C Electrical Data and Timing
          1. 6.16.3.1.1 I2C Timing Requirements
          2. 6.16.3.1.2 I2C Switching Characteristics
          3. 6.16.3.1.3 I2C Timing Diagram
      4. 6.16.4 Power Management Bus (PMBus) Interface
        1. 6.16.4.1 PMBus Electrical Data and Timing
          1. 6.16.4.1.1 PMBus Electrical Characteristics
          2. 6.16.4.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.16.4.1.3 PMBus Standard Mode Switching Characteristics
      5. 6.16.5 Serial Communications Interface (SCI)
      6. 6.16.6 Serial Peripheral Interface (SPI)
        1. 6.16.6.1 SPI Master Mode Timings
          1. 6.16.6.1.1 SPI Master Mode Timing Requirements
          2. 6.16.6.1.2 SPI Master Mode Switching Characteristics - Clock Phase 0
          3. 6.16.6.1.3 SPI Master Mode Switching Characteristics - Clock Phase 1
          4. 6.16.6.1.4 SPI Master Mode Timing Diagrams
        2. 6.16.6.2 SPI Slave Mode Timings
          1. 6.16.6.2.1 SPI Slave Mode Timing Requirements
          2. 6.16.6.2.2 SPI Slave Mode Switching Characteristics
          3. 6.16.6.2.3 SPI Slave Mode Timing Diagrams
      7. 6.16.7 Local Interconnect Network (LIN)
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
      2. 7.3.2 Flash Memory Map
      3. 7.3.3 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  C28x Processor
      1. 7.5.1 Floating-Point Unit (FPU)
      2. 7.5.2 Trigonometric Math Unit (TMU)
      3. 7.5.3 VCRC Unit
      4. 7.5.4 Lockstep Compare Module (LCM)
    6. 7.6  Device Boot Modes
      1. 7.6.1 Device Boot Configurations
        1. 7.6.1.1 Configuring Boot Mode Pins
        2. 7.6.1.2 Configuring Boot Mode Table Options
      2. 7.6.2 GPIO Assignments
    7. 7.7  Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8  Watchdog
    9. 7.9  C28x Timers
    10. 7.10 Dual-Clock Comparator (DCC)
      1. 7.10.1 Features
      2. 7.10.2 Mapping of DCCx Clock Source Inputs
    11. 7.11 Functional Safety
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 On-Board Charger (OBC)
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 OBC Resources
        2. 8.3.1.2 Automotive Pump
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Automotive Pump Resources
        3. 8.3.1.3 Positive Temperature Coefficient (PTC) Heater
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 PTC Resources
        4. 8.3.1.4 Automotive HVAC Compressor
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 Automotive HVAC Compressor Resources
        5. 8.3.1.5 Single-Phase Line-Interactive Uninterruptable Power Supply (UPS)
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 Single-Phase Line-Interactive UPS Resources
        6. 8.3.1.6 AC Drive Power Stage Module
          1. 8.3.1.6.1 System Block Diagram
          2. 8.3.1.6.2 AC Drive Power Stage Module Resources
        7. 8.3.1.7 Server or Telecom Power Supply Unit (PSU)
          1. 8.3.1.7.1 System Block Diagram
          2. 8.3.1.7.2 Server or Telecom PSU Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PM|64
  • RHB|32
  • PN|80
  • PHP|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.13.1.6.2 Power Management Module Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VVREG Internal Voltage Regulator Output 1.152 1.2 1.248 V
VVREG-PU Internal Voltage Regulator Power Up Time 350 us
VVREG-INRUSH(5) Internal Voltage Regulator Inrush Current 650 mA
VPOR-VDDIO VDDIO Power on Reset Voltage Before and After XRSn Release 2.3 V
VBOR-VDDIO-UP(1) VDDIO Brown Out Reset Voltage on Ramp Up Before XRSn Release 2.7 V
VBOR-VDDIO-DOWN(1) VDDIO Brown Out Reset Voltage on Ramp Down After XRSn Release 2.81 3.0 V
VPOR-VDD-UP(2) VDD Power on Reset Voltage on Ramp-Up Before XRSn Release 1 V
VPOR-VDD-DOWN(2) VDD Power on Reset Voltage on Ramp-Down After XRSn Release 1 V
VXRSn-PU-DELAY(3) XRSn Release Delay after Supplies are Ramped Up During Power-Up 40 us
VXRSn-PD-DELAY(4) XRSn Trip Delay after Supplies are Ramped Down During Power-Down 2 us
VDDIO-MON-TOT-DELAY Total Delays in Path of VDDIO Monitors (POR, BOR) 80 us
VXRSn-MON-RELEASE-DELAY XRSn Release Delay after a VDD POR Event Supplies Within Operating Range 40 us
XRSn Release Delay after a VDDIO BOR Event 40 us
XRSn Release Delay after a VDDIO POR Event 120 us
(1) See the Supply Voltages figure.
(2) VPOR-VDD is significantly below the recommended operating conditions. If monitoring of VDD is needed, an external supervisor is required.
(3) Supplies are considered fully ramped up after they cross the minimum recommended operating conditions for the respective rail. All POR and BOR monitors need to be released before this delay takes effect. RC network delay will add to this.
(4) On power down, any of the POR or BOR monitors that trips will immediately trip XRSn. This delay is the time between any of the POR, BOR monitors tripping and XRSn going low. It is variable and depends on the ramp down rate of the supply. RC network delay will add to this.
(5) This is the transient current drawn on the VDDIO rail when the internal VREG turns on. Due to this, there might be some voltage drops on the VDDIO rail when the VREG turns on which could cause the VREG to ramp up in steps. There is no detriment to the device from this but the effect can be reduced if desired by using sufficient decoupling capacitors on VDDIO or picking an LDO/DC-DC that can supply this transient current.