SPRSP68B January   2023  – November 2023 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
        1. 5.4.1.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption - VREG Enable - Internal Supply
      2. 6.5.2 System Current Consumption - VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Current Consumption Graphs
      5. 6.5.5 Reducing Current Consumption
        1. 6.5.5.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for PN Package
    8. 6.8  Thermal Resistance Characteristics for PM Package
    9. 6.9  Thermal Resistance Characteristics for PHP Package
    10. 6.10 Thermal Resistance Characteristics for RHB Package
    11. 6.11 Thermal Design Considerations
    12. 6.12 Thermal Design Considerations for AEC-Q100 Grade 0
      1. 6.12.1 Simple Frequency Reduction
      2. 6.12.2 Dynamic Frequency Reduction
      3. 6.12.3 Flash Considerations
    13. 6.13 System
      1. 6.13.1  Power Management Module (PMM)
        1. 6.13.1.1 Introduction
        2. 6.13.1.2 Overview
          1. 6.13.1.2.1 Power Rail Monitors
            1. 6.13.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.13.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.13.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.13.1.2.2 External Supervisor Usage
          3. 6.13.1.2.3 Delay Blocks
          4. 6.13.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.13.1.2.5 VREGENZ
        3. 6.13.1.3 External Components
          1. 6.13.1.3.1 Decoupling Capacitors
            1. 6.13.1.3.1.1 VDDIO Decoupling
            2. 6.13.1.3.1.2 VDD Decoupling
        4. 6.13.1.4 Power Sequencing
          1. 6.13.1.4.1 Supply Pins Ganging
          2. 6.13.1.4.2 Signal Pins Power Sequence
          3. 6.13.1.4.3 Supply Pins Power Sequence
            1. 6.13.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.13.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.13.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.13.1.4.3.4 Supply Slew Rate
        5. 6.13.1.5 Recommended Operating Conditions Applicability to the PMM
        6. 6.13.1.6 Power Management Module Electrical Data and Timing
          1. 6.13.1.6.1 Power Management Module Operating Conditions
          2. 6.13.1.6.2 Power Management Module Characteristics
      2. 6.13.2  Reset Timing
        1. 6.13.2.1 Reset Sources
        2. 6.13.2.2 Reset Electrical Data and Timing
          1. 6.13.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.13.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.13.2.2.3 Reset Timing Diagrams
      3. 6.13.3  Clock Specifications
        1. 6.13.3.1 Clock Sources
        2. 6.13.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.13.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.13.3.2.1.1 Input Clock Frequency
            2. 6.13.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.13.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.13.3.2.1.4 X1 Timing Requirements
            5. 6.13.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.13.3.2.1.6 APLL Characteristics
            7. 6.13.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.13.3.2.1.8 Internal Clock Frequencies
        3. 6.13.3.3 Input Clocks and PLLs
        4. 6.13.3.4 XTAL Oscillator
          1. 6.13.3.4.1 Introduction
          2. 6.13.3.4.2 Overview
            1. 6.13.3.4.2.1 Electrical Oscillator
              1. 6.13.3.4.2.1.1 Modes of Operation
                1. 6.13.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.13.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.13.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.13.3.4.2.2 Quartz Crystal
            3. 6.13.3.4.2.3 GPIO Modes of Operation
          3. 6.13.3.4.3 Functional Operation
            1. 6.13.3.4.3.1 ESR – Effective Series Resistance
            2. 6.13.3.4.3.2 Rneg – Negative Resistance
            3. 6.13.3.4.3.3 Start-up Time
              1. 6.13.3.4.3.3.1 X1/X2 Precondition
            4. 6.13.3.4.3.4 DL – Drive Level
          4. 6.13.3.4.4 How to Choose a Crystal
          5. 6.13.3.4.5 Testing
          6. 6.13.3.4.6 Common Problems and Debug Tips
          7. 6.13.3.4.7 Crystal Oscillator Specifications
            1. 6.13.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.13.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.13.3.4.7.3 Crystal Oscillator Parameters
            4. 6.13.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 6.13.3.5 Internal Oscillators
          1. 6.13.3.5.1 INTOSC Characteristics
          2. 6.13.3.5.2 INTOSC2 with External Precision Resistor – ExtR
      4. 6.13.4  Flash Parameters
        1. 6.13.4.1 Flash Parameters 
      5. 6.13.5  RAM Specifications
      6. 6.13.6  ROM Specifications
      7. 6.13.7  Emulation/JTAG
        1. 6.13.7.1 JTAG Electrical Data and Timing
          1. 6.13.7.1.1 JTAG Timing Requirements
          2. 6.13.7.1.2 JTAG Switching Characteristics
          3. 6.13.7.1.3 JTAG Timing Diagram
        2. 6.13.7.2 cJTAG Electrical Data and Timing
          1. 6.13.7.2.1 cJTAG Timing Requirements
          2. 6.13.7.2.2 cJTAG Switching Characteristics
          3. 6.13.7.2.3 cJTAG Timing Diagram
      8. 6.13.8  GPIO Electrical Data and Timing
        1. 6.13.8.1 GPIO – Output Timing
          1. 6.13.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.13.8.1.2 General-Purpose Output Timing Diagram
        2. 6.13.8.2 GPIO – Input Timing
          1. 6.13.8.2.1 General-Purpose Input Timing Requirements
          2. 6.13.8.2.2 Sampling Mode
        3. 6.13.8.3 Sampling Window Width for Input Signals
      9. 6.13.9  Interrupts
        1. 6.13.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.13.9.1.1 External Interrupt Timing Requirements
          2. 6.13.9.1.2 External Interrupt Switching Characteristics
          3. 6.13.9.1.3 External Interrupt Timing
      10. 6.13.10 Low-Power Modes
        1. 6.13.10.1 Clock-Gating Low-Power Modes
        2. 6.13.10.2 Low-Power Mode Wake-up Timing
          1. 6.13.10.2.1 IDLE Mode Timing Requirements
          2. 6.13.10.2.2 IDLE Mode Switching Characteristics
          3. 6.13.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.13.10.2.4 STANDBY Mode Timing Requirements
          5. 6.13.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.13.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.13.10.2.7 HALT Mode Timing Requirements
          8. 6.13.10.2.8 HALT Mode Switching Characteristics
          9. 6.13.10.2.9 HALT Entry and Exit Timing Diagram
    14. 6.14 Analog Peripherals
      1. 6.14.1 Analog Pins and Internal Connections
      2. 6.14.2 Analog Signal Descriptions
      3. 6.14.3 Analog-to-Digital Converter (ADC)
        1. 6.14.3.1 ADC Configurability
          1. 6.14.3.1.1 Signal Mode
        2. 6.14.3.2 ADC Electrical Data and Timing
          1. 6.14.3.2.1 ADC Operating Conditions
          2. 6.14.3.2.2 ADC Characteristics
          3. 6.14.3.2.3 ADC Performance Per Pin
          4. 6.14.3.2.4 ADC Input Model
          5. 6.14.3.2.5 ADC Timing Diagrams
      4. 6.14.4 Temperature Sensor
        1. 6.14.4.1 Temperature Sensor Electrical Data and Timing
          1. 6.14.4.1.1 Temperature Sensor Characteristics
      5. 6.14.5 Comparator Subsystem (CMPSS)
        1. 6.14.5.1 CMPSS Module Variants
        2. 6.14.5.2 CMPx_DACL
        3. 6.14.5.3 CMPSS Connectivity Diagram
        4. 6.14.5.4 Block Diagrams
        5. 6.14.5.5 CMPSS Electrical Data and Timing
          1. 6.14.5.5.1 CMPSS Comparator Electrical Characteristics
          2. 6.14.5.5.2 CMPSS_LITE Comparator Electrical Characteristics
          3.        CMPSS Comparator Input Referred Offset and Hysteresis
          4. 6.14.5.5.3 CMPSS DAC Static Electrical Characteristics
          5. 6.14.5.5.4 CMPSS_LITE DAC Static Electrical Characteristics
          6. 6.14.5.5.5 CMPSS Illustrative Graphs
          7. 6.14.5.5.6 CMPSS DAC Dynamic Error
          8. 6.14.5.5.7 Buffered Output from CMPx_DACL Operating Conditions
          9. 6.14.5.5.8 Buffered Output from CMPx_DACL Electrical Characteristics
    15. 6.15 Control Peripherals
      1. 6.15.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.15.1.1 Control Peripherals Synchronization
        2. 6.15.1.2 ePWM Electrical Data and Timing
          1. 6.15.1.2.1 ePWM Timing Requirements
          2. 6.15.1.2.2 ePWM Switching Characteristics
          3. 6.15.1.2.3 Trip-Zone Input Timing
            1. 6.15.1.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.15.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.15.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.15.2.1 HRPWM Electrical Data and Timing
          1. 6.15.2.1.1 High-Resolution PWM Characteristics
      3. 6.15.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.15.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.15.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.15.4 Enhanced Capture (eCAP)
        1. 6.15.4.1 eCAP Block Diagram
        2. 6.15.4.2 eCAP Synchronization
        3. 6.15.4.3 eCAP Electrical Data and Timing
          1. 6.15.4.3.1 eCAP Timing Requirements
          2. 6.15.4.3.2 eCAP Switching Characteristics
      5. 6.15.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.15.5.1 eQEP Electrical Data and Timing
          1. 6.15.5.1.1 eQEP Timing Requirements
          2. 6.15.5.1.2 eQEP Switching Characteristics
    16. 6.16 Communications Peripherals
      1. 6.16.1 Controller Area Network (CAN)
      2. 6.16.2 Modular Controller Area Network (MCAN)
      3. 6.16.3 Inter-Integrated Circuit (I2C)
        1. 6.16.3.1 I2C Electrical Data and Timing
          1. 6.16.3.1.1 I2C Timing Requirements
          2. 6.16.3.1.2 I2C Switching Characteristics
          3. 6.16.3.1.3 I2C Timing Diagram
      4. 6.16.4 Power Management Bus (PMBus) Interface
        1. 6.16.4.1 PMBus Electrical Data and Timing
          1. 6.16.4.1.1 PMBus Electrical Characteristics
          2. 6.16.4.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.16.4.1.3 PMBus Standard Mode Switching Characteristics
      5. 6.16.5 Serial Communications Interface (SCI)
      6. 6.16.6 Serial Peripheral Interface (SPI)
        1. 6.16.6.1 SPI Master Mode Timings
          1. 6.16.6.1.1 SPI Master Mode Timing Requirements
          2. 6.16.6.1.2 SPI Master Mode Switching Characteristics - Clock Phase 0
          3. 6.16.6.1.3 SPI Master Mode Switching Characteristics - Clock Phase 1
          4. 6.16.6.1.4 SPI Master Mode Timing Diagrams
        2. 6.16.6.2 SPI Slave Mode Timings
          1. 6.16.6.2.1 SPI Slave Mode Timing Requirements
          2. 6.16.6.2.2 SPI Slave Mode Switching Characteristics
          3. 6.16.6.2.3 SPI Slave Mode Timing Diagrams
      7. 6.16.7 Local Interconnect Network (LIN)
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
      2. 7.3.2 Flash Memory Map
      3. 7.3.3 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  C28x Processor
      1. 7.5.1 Floating-Point Unit (FPU)
      2. 7.5.2 Trigonometric Math Unit (TMU)
      3. 7.5.3 VCRC Unit
      4. 7.5.4 Lockstep Compare Module (LCM)
    6. 7.6  Device Boot Modes
      1. 7.6.1 Device Boot Configurations
        1. 7.6.1.1 Configuring Boot Mode Pins
        2. 7.6.1.2 Configuring Boot Mode Table Options
      2. 7.6.2 GPIO Assignments
    7. 7.7  Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8  Watchdog
    9. 7.9  C28x Timers
    10. 7.10 Dual-Clock Comparator (DCC)
      1. 7.10.1 Features
      2. 7.10.2 Mapping of DCCx Clock Source Inputs
    11. 7.11 Functional Safety
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 On-Board Charger (OBC)
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 OBC Resources
        2. 8.3.1.2 Automotive Pump
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Automotive Pump Resources
        3. 8.3.1.3 Positive Temperature Coefficient (PTC) Heater
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 PTC Resources
        4. 8.3.1.4 Automotive HVAC Compressor
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 Automotive HVAC Compressor Resources
        5. 8.3.1.5 Single-Phase Line-Interactive Uninterruptable Power Supply (UPS)
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 Single-Phase Line-Interactive UPS Resources
        6. 8.3.1.6 AC Drive Power Stage Module
          1. 8.3.1.6.1 System Block Diagram
          2. 8.3.1.6.2 AC Drive Power Stage Module Resources
        7. 8.3.1.7 Server or Telecom Power Supply Unit (PSU)
          1. 8.3.1.7.1 System Block Diagram
          2. 8.3.1.7.2 Server or Telecom PSU Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PM|64
  • PN|80
  • PHP|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3.2 Digital Signals

Table 5-3 Digital Signals
SIGNAL NAME PIN TYPE DESCRIPTION GPIO 80 PN 64 PM 48 PHP 32 RHB
ADCSOCAO O ADC Start of Conversion A for External ADC 8, 33, 228 10, 38, 58 6, 32, 47 4, 25 2
ADCSOCBO O ADC Start of Conversion B for External ADC 10, 32 49, 76 40, 63 32 20
CANA_RX I CAN-A Receive 0, 3, 5, 11, 12, 18, 21, 30, 33, 35, 49, 230, 242 1, 12, 29, 32, 34, 36, 37, 38, 48, 50, 60, 63, 74 8, 25, 28, 30, 31, 32, 39, 41, 49, 52, 61 5, 21, 24, 25, 31, 33, 39, 42, 47 3, 13, 14, 19, 21, 26, 28, 30
CANA_TX O CAN-A Transmit 2, 4, 7, 13, 17, 19, 20, 31, 32, 37, 48, 224, 228 2, 10, 13, 31, 33, 35, 40, 46, 49, 51, 59, 61, 68 6, 9, 27, 29, 34, 37, 40, 42, 48, 50, 57 4, 6, 22, 23, 29, 32, 34, 38, 40, 43 2, 4, 17, 20, 22, 29
EPWM1_A O ePWM-1 Output A 0, 4, 30, 224 1, 13, 59, 63 9, 48, 52 6, 38, 42 4, 28
EPWM1_B O ePWM-1 Output B 1, 5, 31, 226 2, 11, 62, 74 7, 51, 61 4, 41, 47 2, 27, 30
EPWM2_A O ePWM-2 Output A 2, 6, 7, 41, 230 29, 61, 66, 68, 80 25, 50, 55, 57, 64 21, 40, 43, 48 13, 29
EPWM2_B O ePWM-2 Output B 3, 7, 40, 227, 228 10, 28, 60, 64, 68 6, 24, 49, 53, 57 4, 20, 39, 43 2, 13, 26, 29
EPWM3_A O ePWM-3 Output A 0, 4, 14, 227 28, 59, 63, 79 24, 48, 52 20, 38, 42 13, 28
EPWM3_B O ePWM-3 Output B 1, 5, 15, 230 29, 62, 74, 78 25, 51, 61 21, 41, 47 13, 27, 30
EPWM4_A O ePWM-4 Output A 2, 6, 22, 24, 242 12, 41, 61, 67, 80 8, 35, 50, 56, 64 5, 27, 40, 48 3, 15
EPWM4_B O ePWM-4 Output B 3, 7, 23, 32 49, 60, 65, 68 40, 49, 54, 57 32, 39, 43 20, 26, 29
EPWM5_A O ePWM-5 Output A 8, 16, 37 39, 46, 58 33, 37, 47 26, 29 17
EPWM5_B O ePWM-5 Output B 9, 17, 35 40, 48, 75 34, 39, 62 31 19
EPWM6_A O ePWM-6 Output A 10, 17, 18, 226 11, 40, 50, 76 7, 34, 41, 63 4, 33 2, 21
EPWM6_B O ePWM-6 Output B 11, 19 37, 51 31, 42 34 14, 22
EPWM7_A O ePWM-7 Output A 12, 28, 41 4, 36, 66 2, 30, 55 2, 24 32
EPWM7_B O ePWM-7 Output B 13, 29 3, 35 1, 29 1, 23 31
EQEP1_A I eQEP-1 Input A 6, 10, 20, 25, 28, 35, 40, 44, 224 4, 13, 33, 42, 48, 64, 69, 76, 80 2, 9, 27, 39, 53, 63, 64 2, 6, 22, 31, 44, 48 4, 19, 32
EQEP1_B I eQEP-1 Input B 7, 11, 21, 29, 37, 41, 228 3, 10, 34, 37, 46, 66, 68 1, 6, 28, 31, 37, 55, 57 1, 4, 29, 43 2, 14, 17, 29, 31
EQEP1_INDEX I/O eQEP-1 Index 0, 9, 13, 17, 23, 31, 32, 39, 43, 242 2, 12, 35, 40, 49, 54, 63, 65, 75 8, 29, 34, 40, 52, 54, 62 5, 23, 32, 42 3, 20, 28
EQEP1_STROBE I/O eQEP-1 Strobe 1, 8, 12, 16, 22, 30, 42, 226 1, 11, 36, 39, 57, 58, 62, 67 7, 30, 33, 47, 51, 56 4, 24, 26, 41 2, 27
EQEP2_A I eQEP-2 Input A 11, 14, 18, 24 37, 41, 50, 79 31, 35, 41 27, 33 14, 15, 21
EQEP2_B I eQEP-2 Input B 15, 16, 19, 25, 33 38, 39, 42, 51, 78 32, 33, 42 25, 26, 34 22
EQEP2_INDEX I/O eQEP-2 Index 26, 29, 39 3, 43 1 1 31
EQEP2_STROBE I/O eQEP-2 Strobe 4, 27, 28 4, 44, 59 2, 48 2, 38 32
ERRORSTS O Error Status Output. This signal requires an external pulldown. 24, 28, 29 3, 4, 41 1, 2, 35 1, 2, 27 15, 31, 32
ExtR I External resistor for internal oscillator. This can be used for greater clock accuracy. 19 51 42 34 22
GPIO0 I/O General-Purpose Input Output 0 0 63 52 42 28
GPIO1 I/O General-Purpose Input Output 1 1 62 51 41 27
GPIO2 I/O General-Purpose Input Output 2 2 61 50 40
GPIO3 I/O General-Purpose Input Output 3 3 60 49 39 26
GPIO4 I/O General-Purpose Input Output 4 4 59 48 38
GPIO5 I/O General-Purpose Input Output 5 5 74 61 47 30
GPIO6 I/O General-Purpose Input Output 6 6 80 64 48
GPIO7 I/O General-Purpose Input Output 7 7 68 57 43 29
GPIO8 I/O General-Purpose Input Output 8 8 58 47
GPIO9 I/O General-Purpose Input Output 9 9 75 62
GPIO10 I/O General-Purpose Input Output 10 10 76 63
GPIO11 I/O General-Purpose Input Output 11 11 37 31 14
GPIO12 I/O General-Purpose Input Output 12 12 36 30 24
GPIO13 I/O General-Purpose Input Output 13 13 35 29 23
GPIO14 I/O General-Purpose Input Output 14 14 79
GPIO15 I/O General-Purpose Input Output 15 15 78
GPIO16 I/O General-Purpose Input Output 16 16 39 33 26
GPIO17 I/O General-Purpose Input Output 17 17 40 34
GPIO18 I/O General-Purpose Input Output 18 18 50 41 33 21
GPIO19 I/O General-Purpose Input Output 19 19 51 42 34 22
GPIO20 I/O General-Purpose Input Output 20 20 33 27 22
GPIO21 I/O General-Purpose Input Output 21 21 34 28
GPIO22 I/O General-Purpose Input Output 22 22 67 56
GPIO23 I/O General-Purpose Input Output 23 23 65 54
GPIO24 I/O General-Purpose Input Output 24 24 41 35 27 15
GPIO25 I/O General-Purpose Input Output 25 25 42
GPIO26 I/O General-Purpose Input Output 26 26 43
GPIO27 I/O General-Purpose Input Output 27 27 44
GPIO28 I/O General-Purpose Input Output 28 28 4 2 2 32
GPIO29 I/O General-Purpose Input Output 29 29 3 1 1 31
GPIO30 I/O General-Purpose Input Output 30 30 1
GPIO31 I/O General-Purpose Input Output 31 31 2
GPIO32 I/O General-Purpose Input Output 32 32 49 40 32 20
GPIO33 I/O General-Purpose Input Output 33 33 38 32 25
GPIO34 I/O General-Purpose Input Output 34 34 77
GPIO35 I/O General-Purpose Input Output 35 35 48 39 31 19
GPIO37 I/O General-Purpose Input Output 37 37 46 37 29 17
GPIO39 I/O General-Purpose Input Output 39 39
GPIO40 I/O General-Purpose Input Output 40 40 64 53
GPIO41 I/O General-Purpose Input Output 41 41 66 55
GPIO42 I/O General-Purpose Input Output 42 42 57
GPIO43 I/O General-Purpose Input Output 43 43 54
GPIO44 I/O General-Purpose Input Output 44 44 69 44
GPIO45 I/O General-Purpose Input Output 45 45 73
GPIO46 I/O General-Purpose Input Output 46 46 6
GPIO48 I/O General-Purpose Input Output 48 48 31
GPIO49 I/O General-Purpose Input Output 49 49 32
GPIO224 I/O General-Purpose Input Output 224 224 13 9 6 4
GPIO226 I/O General-Purpose Input Output 226 226 11 7 4 2
GPIO227 I/O General-Purpose Input Output 227 227 28 24 20 13
GPIO228 I/O General-Purpose Input Output 228 228 10 6 4 2
GPIO230 I/O General-Purpose Input Output 230 230 29 25 21 13
GPIO242 I/O General-Purpose Input Output 242 242 12 8 5 3
I2CA_SCL I/OD I2C-A Open-Drain Bidirectional Clock 1, 4, 8, 18, 20, 27, 33, 37, 43 33, 38, 44, 46, 50, 54, 58, 59, 62 27, 32, 37, 41, 47, 48, 51 22, 25, 29, 33, 38, 41 17, 21, 27
I2CA_SDA I/OD I2C-A Open-Drain Bidirectional Data 0, 5, 10, 19, 21, 26, 32, 35, 42, 230 29, 34, 43, 48, 49, 51, 57, 63, 74, 76 25, 28, 39, 40, 42, 52, 61, 63 21, 31, 32, 34, 42, 47 13, 19, 20, 22, 28, 30
I2CB_SCL I/OD I2C-B Open-Drain Bidirectional Clock 3, 9, 15, 29, 227 3, 28, 60, 75, 78 1, 24, 49, 62 1, 20, 39 13, 26, 31
I2CB_SDA I/OD I2C-B Open-Drain Bidirectional Data 2, 14, 28, 34, 230 4, 29, 61, 77, 79 2, 25, 50 2, 21, 40 13, 32
LINA_RX I LIN-A Receive 23, 29, 33, 35, 42, 49, 226 3, 11, 32, 38, 48, 57, 65 1, 7, 32, 39, 54 1, 4, 25, 31 2, 19, 31
LINA_TX O LIN-A Transmit 22, 28, 32, 37, 46 4, 6, 46, 49, 67 2, 37, 40, 56 2, 29, 32 17, 20, 32
MCAN_RX I CAN/CAN FD Receive 0, 5, 12, 21, 30, 39, 49 1, 32, 34, 36, 63, 74 28, 30, 52, 61 24, 42, 47 28, 30
MCAN_TX O CAN/CAN FD Transmit 1, 4, 13, 20, 31, 46, 48 2, 6, 31, 33, 35, 59, 62 27, 29, 48, 51 22, 23, 38, 41 27
OUTPUTXBAR1 O Output X-BAR Output 1 2, 24, 34, 227 28, 41, 61, 77 24, 35, 50 20, 27, 40 13, 15
OUTPUTXBAR2 O Output X-BAR Output 2 3, 25, 37, 242 12, 42, 46, 60 8, 37, 49 5, 29, 39 3, 17, 26
OUTPUTXBAR3 O Output X-BAR Output 3 4, 5, 14, 26, 48, 224 13, 31, 43, 59, 74, 79 9, 48, 61 6, 38, 47 4, 30
OUTPUTXBAR4 O Output X-BAR Output 4 6, 15, 27, 33, 49 32, 38, 44, 78, 80 32, 64 25, 48
OUTPUTXBAR5 O Output X-BAR Output 5 7, 28, 42 4, 57, 68 2, 57 2, 43 29, 32
OUTPUTXBAR6 O Output X-BAR Output 6 9, 29, 43 3, 54, 75 1, 62 1 31
OUTPUTXBAR7 O Output X-BAR Output 7 0, 11, 16, 30, 44 1, 37, 39, 63, 69 31, 33, 52 26, 42, 44 14, 28
OUTPUTXBAR8 O Output X-BAR Output 8 17, 31, 45 2, 40, 73 34
PMBUSA_ALERT I/OD PMBus-A Open-Drain Bidirectional Alert Signal 13, 19, 27, 37, 43, 45 35, 44, 46, 51, 54, 73 29, 37, 42 23, 29, 34 17, 22
PMBUSA_CTL I/O PMBus-A Control Signal - Slave Input/Master Output 12, 18, 26, 35, 42, 44 36, 43, 48, 50, 57, 69 30, 39, 41 24, 31, 33, 44 19, 21
PMBUSA_SCL I/OD PMBus-A Open-Drain Bidirectional Clock 3, 15, 16, 24, 35, 41, 230 29, 39, 41, 48, 60, 66, 78 25, 33, 35, 39, 49, 55 21, 26, 27, 31, 39 13, 15, 19, 26
PMBUSA_SDA I/OD PMBus-A Open-Drain Bidirectional Data 2, 14, 17, 25, 32, 34, 40, 44, 46, 48 6, 31, 40, 42, 49, 61, 64, 69, 77, 79 34, 40, 50, 53 32, 40, 44 20
SCIA_RX I SCI-A Receive Data 0, 3, 5, 9, 17, 25, 28, 35, 49 4, 32, 40, 42, 48, 60, 63, 74, 75 2, 34, 39, 49, 52, 61, 62 2, 31, 39, 42, 47 19, 26, 28, 30, 32
SCIA_TX O SCI-A Transmit Data 1, 2, 7, 8, 16, 24, 29, 37, 48 3, 31, 39, 41, 46, 58, 61, 62, 68 1, 33, 35, 37, 47, 50, 51, 57 1, 26, 27, 29, 40, 41, 43 15, 17, 27, 29, 31
SCIB_RX I SCI-B Receive Data 11, 13, 15, 19, 23, 41 35, 37, 51, 65, 66, 78 29, 31, 42, 54, 55 23, 34 14, 22
SCIB_TX O SCI-B Transmit Data 9, 10, 12, 14, 18, 22, 40 36, 50, 64, 67, 75, 76, 79 30, 41, 53, 56, 62, 63 24, 33 21
SCIC_RX I SCI-C Receive Data 21, 42, 226 11, 34, 57 7, 28 4 2
SCIC_TX O SCI-C Transmit Data 20, 43, 224 13, 33, 54 9, 27 6, 22 4
SPIA_CLK I/O SPI-A Clock 3, 9, 12, 18, 28, 32, 226 4, 11, 36, 49, 50, 60, 75 2, 7, 30, 40, 41, 49, 62 2, 4, 24, 32, 33, 39 2, 20, 21, 26, 32
SPIA_SIMO I/O SPI-A Slave In, Master Out (SIMO) 2, 7, 8, 11, 16, 20, 24, 224 13, 33, 37, 39, 41, 58, 61, 68 9, 27, 31, 33, 35, 47, 50, 57 6, 22, 26, 27, 40, 43 4, 14, 15, 29
SPIA_SOMI I/O SPI-A Slave Out, Master In (SOMI) 1, 4, 10, 13, 17, 21, 35, 228 10, 34, 35, 40, 48, 59, 62, 76 6, 28, 29, 34, 39, 48, 51, 63 4, 23, 31, 38, 41 2, 19, 27
SPIA_STE I/O SPI-A Slave Transmit Enable (STE) 0, 5, 11, 19, 24, 29, 37, 242 3, 12, 37, 41, 46, 51, 63, 74 1, 8, 31, 35, 37, 42, 52, 61 1, 5, 27, 29, 34, 42, 47 3, 14, 15, 17, 22, 28, 30, 31
SYNCOUT O External ePWM Synchronization Pulse 6, 39 80 64 48
TDI I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input. 35 48 39 31 19
TDO O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input. 37 46 37 29 17
X1 I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock. 19 51 42 34 22
X2 I/O Crystal oscillator output. 18 50 41 33 21
XCLKOUT O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device. 16, 18 39, 50 33, 41 26, 33 21