SPRSP68B January 2023 – November 2023 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1
PRODMIX
Refer to the PDF data sheet for device specific package drawings
For applications that do not need to use all functions of the device, Table 5-10 lists acceptable conditioning for any unused pins. When multiple options are listed in Table 5-10, any option is acceptable. Pins not listed in Table 5-10 must be connected according to Section 5.
SIGNAL NAME | ACCEPTABLE PRACTICE |
---|---|
ANALOG | |
VREFHI | Tie to VDDA (applies only if ADC is not used in the application) |
VREFLO | Tie to VSSA |
Analog input pins |
|
Analog input pins (shared with GPIO) |
|
DIGITAL | |
GPIOx |
|
GPIO35/TDI | When TDI mux option is selected
(default), the GPIO is in Input mode.
|
GPIO37/TDO | When TDO mux option is selected
(default), the GPIO is in Output mode only during
JTAG activity; otherwise, it is in a tri-state
condition. The pin must be biased to avoid extra
current on the input buffer.
|
TCK |
|
TMS | Pullup resistor |
GPIO19/X1 | Turn XTAL off and:
|
GPIO18/X2 | Turn XTAL off and:
|
POWER AND GROUND | |
VDD | All VDD pins must be connected per Section 5.3. Pins should not be used to bias any external circuits. |
VDDA | If a dedicated analog supply is not used, tie to VDDIO. |
VDDIO | All VDDIO pins must be connected per Section 5.3. |
VSS | All VSS pins must be connected to board ground. |
VSSA | If an analog ground is not used, tie to VSS. |