SCDS414F december   2019  – july 2023 TMUX1308-Q1 , TMUX1309-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: TMUX1308-Q1
    5. 7.5  Thermal Information: TMUX1309-Q1
    6. 7.6  Electrical Characteristics
    7. 7.7  Logic and Dynamic Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Injection Current Coupling
    10. 7.10 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1  On-Resistance
    2. 8.2  Off-Leakage Current
    3. 8.3  On-Leakage Current
    4. 8.4  Transition Time
    5. 8.5  Break-Before-Make
    6. 8.6  tON(EN) and tOFF(EN)
    7. 8.7  Charge Injection
    8. 8.8  Off Isolation
    9. 8.9  Crosstalk
    10. 8.10 Bandwidth
    11. 8.11 Injection Current Control
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Bidirectional Operation
      2. 9.3.2 Rail-to-Rail Operation
      3. 9.3.3 1.8 V Logic Compatible Inputs
      4. 9.3.4 Fail-Safe Logic
      5. 9.3.5 Injection Current Control
        1. 9.3.5.1 TMUX13xx-Q1 is Powered, Channel is Unselected, and the Input Signal is Greater Than VDD (VDD = 5 V, VINPUT = 5.5 V)
        2. 9.3.5.2 TMUX13xx-Q1 is Powered, Channel is Selected, and the Input Signal is Greater Than VDD (VDD = 5 V, VINPUT = 5.5 V)
        3. 9.3.5.3 TMUX13xx-Q1 is Unpowered and the Input Signal has a Voltage Present (VDD = 0 V, VINPUT = 3 V)
    4. 9.4 Device Functional Modes
    5. 9.5 Truth Tables
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Short To Battery Protection
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-9358E639-3743-40F1-8BBE-F5BFB42F10C1-low.svgFigure 6-1 TMUX1308-Q1: PW Package,16-Pin TSSOP(Top View)
GUID-FFC68698-A64B-42D6-ADD9-B4CDC3B1C469-low.svgFigure 6-2 TMUX1308-Q1: DYY Package,16-Pin SOT-23-THIN(Top View)
GUID-21A6D47B-80BD-46C7-A8B4-A8278BC53835-low.svg Figure 6-3 TMUX1308-Q1: BQB Package,16-Pin WQFN(Top View)
Table 6-1 Pin Functions TMUX1308-Q1
PIN TYPE(1) DESCRIPTION(2)
NAME NO.
S4 1 I/O Source pin 4. Signal path can be an input or output.
S6 2 I/O Source pin 6. Signal path can be an input or output.
D 3 I/O Drain pin (common). Signal path can be an input or output.
S7 4 I/O Source pin 7. Signal path can be an input or output.
S5 5 I/O Source pin 5. Signal path can be an input or output.
EN 6 I Active low logic input. When this pin is high, all switches are turned off. When this pin is low, the A[2:0] address inputs determine which switch is turned on as listed in Table 9-1.
N.C. 7 Not Connected Not internally connected.
GND 8 P Ground (0 V) reference
A2 9 I Address line 2. Controls the switch configuration as listed in Table 9-1.
A1 10 I Address line 1. Controls the switch configuration as listed in Table 9-1.
A0 11 I Address line 0. Controls the switch configuration as listed in Table 9-1.
S3 12 I/O Source pin 3. Signal path can be an input or output.
S0 13 I/O Source pin 0. Signal path can be an input or output.
S1 14 I/O Source pin 1. Signal path can be an input or output.
S2 15 I/O Source pin 2. Signal path can be an input or output.
VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
Thermal pad — Exposed thermal pad with conductive die attached. No requirement to solder this pad. If connected, then it should be left floating or tied to GND.
(1) I = input, O = output, I/O = input and output, P = power.
(2) For what to do with unused pins, refer to Section 9.4.
GUID-A6E98385-B84B-4A0C-A2EF-E5A8EED26EF0-low.svgFigure 6-4 TMUX1309-Q1: PW Package,16-Pin TSSOP(Top View)
GUID-A7D35D24-DBF0-47FB-847D-39478529BAFD-low.svgFigure 6-5 TMUX1309-Q1: DYY Package,16-Pin SOT-23-THIN(Top View)
GUID-035F8A84-0BC7-44BF-AC07-B082E818D8F2-low.svg Figure 6-6 TMUX1309-Q1: BQB Package,16-Pin WQFN(Top View)
Table 6-2 Pin Functions TMUX1309-Q1
PIN TYPE(1) DESCRIPTION(2)
NAME NO.
S0B 1 I/O Source pin 0 of mux B. Can be an input or output.
S2B 2 I/O Source pin 2 of mux B. Can be an input or output.
DB 3 I/O Drain pin (Common) of mux B. Can be an input or output.
S3B 4 I/O Source pin 3 of mux B. Can be an input or output.
S1B 5 I/O Source pin 1 of mux B. Can be an input or output.
EN 6 I Active low logic input. When this pin is high, all switches are turned off. When this pin is low, the A[1:0] address inputs determine which switch is turned on.
N.C. 7 Not Connected Not internally connected.
GND 8 P Ground (0 V) reference
A1 9 I Address line 1. Controls the switch configuration as listed in Table 9-2.
A0 10 I Address line 0. Controls the switch configuration as listed in Table 9-2.
S3A 11 I/O Source pin 3 of mux A. Can be an input or output.
S0A 12 I/O Source pin 0 of mux A. Can be an input or output.
DA 13 I/O Drain pin (Common) of mux A. Can be an input or output.
S1A 14 I/O Source pin 1 of mux A. Can be an input or output.
S2A 15 I/O Source pin 2 of mux A. Can be an input or output.
VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
Thermal pad — Exposed thermal pad with conductive die attached. No requirement to solder this pad. If connected, then it should be left floating or tied to GND.
(1) I = input, O = output, I/O = input and output, P = power.
(2) For what to do with unused pins, refer to Section 9.4.