SCDS463A June 2022 – March 2023 TMUX4051-Q1 , TMUX4052-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PIN | TYPE(1) | DESCRIPTION(3) | |
---|---|---|---|
NAME | NO. | ||
S4 | 1 | I/O | Source pin 4. Signal path can be an input or output. |
S6 | 2 | I/O | Source pin 6. Signal path can be an input or output. |
D | 3 | I/O | Drain pin (common). Signal path can be an input or output. |
S7 | 4 | I/O | Source pin 7. Signal path can be an input or output. |
S5 | 5 | I/O | Source pin 5. Signal path can be an input or output. |
EN | 6 | I | Active low logic enable. When this pin is high, all switches are turned off. Table 9-1 lists how the A[2:0] address inputs determine which switch is turned on when this pin is low. |
VSS | 7 | P | Negative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. |
GND | 8 | P | Ground (0 V) reference |
A2 | 9 | I | Address line 2. Table 9-1 provides information about how A2 controls the switch configuration. |
A1 | 10 | I | Address line 1. Table 9-1 provides information about how A1 controls the switch configuration. |
A0 | 11 | I | Address line 0. Table 9-1 provides information about how A0 controls the switch configuration. |
S3 | 12 | I/O | Source pin 3. Signal path can be an input or output. |
S0 | 13 | I/O | Source pin 0. Signal path can be an input or output. |
S1 | 14 | I/O | Source pin 1. Signal path can be an input or output. |
S2 | 15 | I/O | Source pin 2. Signal path can be an input or output. |
VDD | 16 | P | Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. |
Thermal pad | — | The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to GND. |
PIN | TYPE(1) | DESCRIPTION(3) | |
---|---|---|---|
NAME | NO. | ||
S0B | 1 | I/O | Source pin 0 of mux B. Can be an input or output. |
S2B | 2 | I/O | Source pin 2 of mux B. Can be an input or output. |
DB | 3 | I/O | Drain pin (common) of mux B. Can be an input or output. |
S3B | 4 | I/O | Source pin 3 of mux B. Can be an input or output. |
S1B | 5 | I/O | Source pin 1 of mux B. Can be an input or output. |
EN | 6 | I | Active low logic enable. When this pin is high, all switches are turned off. When this pin is low, the A[1:0] address inputs determine which switch is turned on. |
VSS | 7 | P | Negative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. |
GND | 8 | P | Ground (0 V) reference |
A1 | 9 | I | Address line 1. Table 9-2 provides information about how A1 controls the switch configuration. |
A0 | 10 | I | Address line 0. Table 9-2 provides information about how A0 controls the switch configuration. |
S3A | 11 | I/O | Source pin 3 of mux A. Can be an input or output. |
S0A | 12 | I/O | Source pin 0 of mux A. Can be an input or output. |
DA | 13 | I/O | Drain pin (common) of mux A. Can be an input or output. |
S1A | 14 | I/O | Source pin 1 of mux A. Can be an input or output. |
S2A | 15 | I/O | Source pin 2 of mux A. Can be an input or output. |
VDD | 16 | P | Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. |
Thermal pad | — | The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to GND. |