SCDS443B October   2022  – June 2024 TMUX7201 , TMUX7202

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Source or Drain Continuous Current
    6. 5.6  ±15V Dual Supply: Electrical Characteristics 
    7. 5.7  ±15V Dual Supply: Switching Characteristics 
    8. 5.8  ±20V Dual Supply: Electrical Characteristics
    9. 5.9  ±20V Dual Supply: Switching Characteristics
    10. 5.10 44V Single Supply: Electrical Characteristics 
    11. 5.11 44V Single Supply: Switching Characteristics 
    12. 5.12 12V Single Supply: Electrical Characteristics 
    13. 5.13 12V Single Supply: Switching Characteristics 
    14. 5.14 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  On-Resistance
    2. 6.2  Off-Leakage Current
    3. 6.3  On-Leakage Current
    4. 6.4  tON and tOFF Time
    5. 6.5  tON (VDD) Time
    6. 6.6  Propagation Delay
    7. 6.7  Charge Injection
    8. 6.8  Off Isolation
    9. 6.9  Bandwidth
    10. 6.10 THD + Noise
    11. 6.11 Power Supply Rejection Ratio (PSRR)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bidirectional Operation
      2. 7.3.2 Rail-to-Rail Operation
      3. 7.3.3 1.8V Logic Compatible Inputs
      4. 7.3.4 Integrated Pull-Down Resistor on Logic Pins
      5. 7.3.5 Fail-Safe Logic
      6. 7.3.6 latch-up Immune
      7. 7.3.7 Ultra-Low Charge Injection
    4. 7.4 Device Functional Modes
    5. 7.5 Truth Tables
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TIA Feedback Gain Switch
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Ultra-Low Charge Injection

Figure 7-1 shows how the TMUX720x devices have a transmission gate topology. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

TMUX7201 TMUX7202 Transmission Gate Topology Figure 7-1 Transmission Gate Topology

The TMUX720x contains specialized architecture to reduce charge injection on the Drain (Dx). To further reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the Source (S). By design, the excess charge from the switch transition will be pushed into the compensation capacitor on the Source (S) instead of the Drain (D). As a general rule, Cp should be 20x larger than the equivalent load capacitance on the Drain (D). Figure 7-2 shows charge injection variation with different compensation capacitors on the Source side. This plot was captured on the TMUX7219 as part of the TMUX72xx family with a 100pF load capacitance.

TMUX7201 TMUX7202 Charge Injection Compensation Figure 7-2 Charge Injection Compensation