SCDS456 January   2024 TMUX7212M

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Source or Drain Continuous Current
    6.     ±15 V Dual Supply: Electrical Characteristics 
    7.     ±15 V Dual Supply: Switching Characteristics 
    8.     ±20 V Dual Supply: Electrical Characteristics
    9.     ±20 V Dual Supply: Switching Characteristics
    10. 44  V Single Supply: Electrical Characteristics 
    11. 44  V Single Supply: Switching Characteristics 
    12. 12  V Single Supply: Electrical Characteristics 
    13. 12  V Single Supply: Switching Characteristics 
    14. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  tON and tOFF Time
    5. 7.5  tON (VDD) Time
    6. 7.6  Propagation Delay
    7. 7.7  Charge Injection
    8. 7.8  Off Isolation
    9. 7.9  Channel-to-Channel Crosstalk
    10. 7.10 Bandwidth
    11. 7.11 THD + Noise
    12. 7.12 Power Supply Rejection Ratio (PSRR)
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8V Logic Compatible Inputs
      4. 8.3.4 Integrated Pull-Down Resistor on Logic Pins
      5. 8.3.5 Fail-Safe Logic
      6. 8.3.6 Latch-Up Immune
      7. 8.3.7 Ultra-Low Charge Injection
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application – Switched Gain Amplifier
    3. 9.3 Design Requirements
    4. 9.4 Detailed Design Procedure
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.7 Ultra-Low Charge Injection

Figure 8-1 shows how the TMUX7212M devices have a transmission gate topology. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

GUID-E509C7FD-0F79-4AD4-9FE9-87F07F01D1E9-low.gif Figure 8-1 Transmission Gate Topology

The TMUX7212M contains specialized architecture to reduce charge injection on the Drain (Dx). To further reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the Source (Sx). This will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the Source (Sx) instead of the Drain (Dx). As a general rule, Cp should be 20x larger than the equivalent load capacitance on the Drain (Dx). Figure 8-2 shows charge injection variation with different compensation capacitors on the Source side. This plot was captured on the TMUX7219M as part of the TMUX72xx family with a 100 pF load capacitance.

GUID-20210729-CA0I-KVFJ-6WNR-N65GRJM9PQW1-low.svg Figure 8-2 Charge Injection Compensation