SCDS434B October   2021  – March 2023 TMUX8211 , TMUX8212 , TMUX8213

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings: TMUX821x Devices
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions: TMUX821x Devices
    4. 7.4  Source of Drain Continuous Current
    5. 7.5  Source of Drain Pulse Current
    6. 7.6  Thermal Information
    7. 7.7  Electrical Characteristics (Global): TMUX821x Devices
    8. 7.8  Electrical Characteristics (±15-V Dual Supply)
    9. 7.9  Electrical Characteristics (±36-V Dual Supply)
    10. 7.10 Electrical Characteristics (±50-V Dual Supply)
    11. 7.11 Electrical Characteristics (72-V Single Supply)
    12. 7.12 Electrical Characteristics (100-V Single Supply)
    13. 7.13 Switching Characteristics: TMUX821x Devices
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 On-Resistance
    2. 8.2 Off-Leakage Current
    3. 8.3 On-Leakage Current
    4. 8.4 Device Turn-On and Turn-Off Time
    5. 8.5 Charge Injection
    6. 8.6 Off Isolation
    7. 8.7 Crosstalk
    8. 8.8 Bandwidth
    9. 8.9 THD + Noise
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Bidirectional Operation
      2. 9.3.2 Flat On-Resistance
      3. 9.3.3 Protection Features
        1. 9.3.3.1 Fail-Safe Logic
        2. 9.3.3.2 ESD Protection
        3. 9.3.3.3 Latch-Up Immunity
      4. 9.3.4 1.8 V Logic Compatible Inputs
      5. 9.3.5 Integrated Pull-Down Resistor on Logic Pins
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Truth Tables
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.3.3 Latch-Up Immunity

Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This condition is caused by a trigger (current injection or over-voltage), but once activated the low impedance path remains even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic damage due to excessive current levels. The Latch-Up condition typically requires a power cycle to eliminate the low impedance path.

In the TMUX821x devices, an insulating oxide layer is placed on top of the silicon substrate to prevent any parasitic junctions from forming. As a result, the devices are Latch-Up immune under all circumstances by device construction.

The TMUX821x devices are constructed on silicon on insulator (SOI) based process where an oxide layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events due to over-voltage or current injections. The Latch-Up immunity feature allows the TMUX821x to be used in harsh environments. For more information on Latch-Up immunity, refer to Using Latch Up Immune Multiplexers to Help Improve System Reliability.