SLLSEB1G February   2012  – August 2024 TPD1E10B06

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings - JEDEC Specification
    3. 5.3 ESD Ratings—IEC Specification
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2. 10.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
VRWM Reverse stand-off voltage Pin 1 to 2 or Pin 2 to 1 5.5 V
ILEAK Leakage current Pin 1 = 5 V, Pin 2 = 0 V 100 nA
VClamp1,2 Clamp voltage with surge strike on pin 1, pin 2 grounded. IPP = 1 A, tp = 8/20 µs(2) 10 V
VClamp1,2 Clamp voltage with surge strike on pin 1, pin 2 grounded. IPP =5 A, tp = 8/20 µs(2) 14 V
VClamp2,1 Clamp voltage with surge strike on pin 2, pin 1 grounded. IPP = 1 A, tp = 8/20 µs(2) 8.5 V
IPP = 5 A, tp = 8/20 µs(2) 14
RDYN Dynamic resistance Pin 1 to Pin 2(1) 0.32 Ω
Pin 2 to Pin 1(1) 0.38
CIO I/O capacitance VIO = 2.5 V;  ƒ = 1 MHz  12 pF
VBR1,2 Break-down voltage, pin 1 to pin 2 IIO = 1 mA 6 V
VBR2,1 Break-down voltage, pin 2 to pin 1 IIO = 1 mA 6 V
(1) Extraction of RDYN using least squares fit of TLP characteristics between IPP = 10 A and IPP = 20 A.
(2) Nonrepetitive current pulse 8 to 20 µs exponentially decaying waveform according to IEC 61000-4-5