SLVSDL1 April   2017 TPD2S300

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—JEDEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 2-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2 Pins): 24-VDC Tolerant
      2. 7.3.2 2-Channels of IEC61000-4-2 ESD Protection (CC1, CC2 Pins)
      3. 7.3.3 Low Quiescent Current: 3.23 µA (Typical), VPWR, VM = 3.3 V
      4. 7.3.4 CC1, CC2 Overvoltage Protection FETs 200 mA Capable for Passing VCONN Power
      5. 7.3.5 CC Dead Battery Resistors Integrated for Handling Dead Battery Use Case in Mobile Devices
      6. 7.3.6 1.4-mm × 1.4-mm WCSP Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Smart-Phone Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 VBIAS Capacitor Selection
          2. 8.2.1.2.2 Dead Battery Operation
          3. 8.2.1.2.3 CC Line Capacitance
          4. 8.2.1.2.4 FLT Pin Operation
          5. 8.2.1.2.5 VCONN Operation
          6. 8.2.1.2.6 Low Quiescent Current
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Laptop Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 VBIAS Capacitor Selection
          2. 8.2.2.2.2 Dead Battery Operation
          3. 8.2.2.2.3 CC Line Capacitance
          4. 8.2.2.2.4 FLT Pin Operation
          5. 8.2.2.2.5 VCONN Operation
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Power Adaptor Application
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 VBIAS Capacitor Selection
          2. 8.2.3.2.2 Dead Battery Operation
          3. 8.2.3.2.3 CC Line Capacitance
          4. 8.2.3.2.4 FLT Pin Operation
          5. 8.2.3.2.5 VCONN Operation
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI Input voltage VPWR –0.3 5.5 V
VM –0.3 28 V
VO Output voltage FLT –0.3 6 V
VBIAS –0.3 24 V
VIO I/O voltage CC1, CC2 –0.3 6 V
C_CC1, C_CC2 –0.3 24 V
TA Operating free air temperature –40 85 °C
TJ Operating junction temperature –40 105 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings—JEDEC Specification

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance.

6.3 ESD Ratings—IEC Specification

VALUE UNIT
V(ESD) Electrostatic discharge IEC 61000-4-2, C_CC1, C_CC2 Contact discharge ±8000 V
Air-gap discharge ±15000

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VI Input voltage VPWR 2.7 3.3 4.5 V
VM 2.7 22 V
VO Output voltage FLT Pull-up resistor power rail 2.7 5.5 V
VIO I/O voltage CC1, CC2, C_CC1, C_CC2 0 5.5 V
IVCONN VCONN current Current flowing from CCx to C_CCx 200 mA
External components(1) FLT Pull-up resistance 1.7 300 kΩ
VBIAS capacitance(2) 0.1 µF
VPWR capacitance, VM capacitance 0.3 1 µF
(1) For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin. Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature variation. The effective value presented must be within the minimum and maximums listed in the table.
(2) The VBIAS pin requires a minimum 35-VDC rated capacitor. A 50-VDC rated capacitor is recommended to reduce capacitance derating. See the VBIAS Capacitor Selection section for more details on VBIAS capacitor selection.

6.5 Thermal Information

THERMAL METRIC(1) TPD2S300 UNIT
YFF (WCSP)
9 PINS
RθJA Junction-to-ambient thermal resistance 107.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.9 °C/W
RθJB Junction-to-board thermal resistance 28.1 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 28.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CC OVP SWITCHES
RON_VCONN_1 On resistance of CC OVP FETs VCONN operation VM = 8.7 V, CCx = 3 V, ICCx = 0.6 A,
–40°C ≤ TJ ≤ 105°C		 0.560 Ω
RON_VCONN_2 On resistance of CC OVP FETs VCONN operation VM = 8.7 V, CCx = 4.87 V, ICCx = 0.2 A, –40°C ≤ TJ ≤ 105°C 0.608 Ω
RON_FRS On resistance of CC OVP FETs fast role swap operation VM = 2.7 V, CCx = 0.49 V, ICCx = 30 mA, –40°C ≤ TJ ≤ 105°C 1.3 Ω
RON_CC_ANA On resistance of CC OVP FETs CC analog operation VM = 2.7 V, CCx = 2.45 V, ICCx = 400 µA, –40°C ≤ TJ ≤ 105°C 18.7 Ω
RON_PD On resistance of CC OVP FETs CC USB-PD operation VM = 2.7 V, CCx = 1.2 V, ICCx = 250 µA, –20°C ≤ TJ ≤ 105°C 13 Ω
RONFLAT_VCONN_1 On resistance flatness of CC OVP FETs VCONN operation VM = 8.7 V, sweep CCx from 0 V to 5.5 V, measure the difference in resistance. ICCx = 0.2 A, –40°C ≤ TJ ≤ 105°C 0.2 Ω
CON_CC Equivalent on capacitance for CC pins Capacitance from C_CCx or CCx to GND when device is powered. VC_CCx/VCCx = 0 V to 1.2 V, f = 400 kHz, –40°C ≤ TJ ≤ 105°C 30 120 pF
VTH_DB Threshold voltage of the pull-down FET in series with RD during dead battery I_C_CCx = 80 uA 0.5 0.9 1.2 V
RD Dead battery pull-down resistance (only present when device is unpowered). Effective resistance of RD and FET in series VPWR = 0 V, VC_CCx = 2.6 V 4.1 5.1 6.1 kΩ
VOVPCC_RISE Rising overvoltage protection threshold on C_CCx pins Place 5.5 V on C_CCx pins. Step up voltage until the FLT pin is asserted .–20°C ≤ TJ ≤ 105°C 5.55 6.18 V
VOVPCC_HYS OVP threshold hysteresis Place 6.5 V on C_CCx. Step down the voltage on C_CCx until the FLT pin is deasserted. Measure the difference between rising and falling OVP thresholds 50 mV
BWON On bandwidth single ended (–3dB) Measure the –3-dB bandwidth from C_CCx to CCx. Single ended measurement, 50-Ω system. Vcm = 0 V to 1.2 V 80 MHz
VSTBUS_CC Short-to-VBUS tolerance on the C_CCx pins Hot-Plug C_CCx with a 1 meter USB Type C Cable. Place a 30-Ω load on CCx 24 V
VSTBUS_CC_CLAMP Short-to-VBUS system-side clamping voltage on the CCx pins Hot-Plug C_CCx with a 1-meter USB Type C Cable. Hot-plug voltage C_CCx = 2 4V. VPWR = 3.3 V. Place a 30-Ω load on CCx 8 V
POWER SUPPLY AND LEAKAGE CURRENTS
VPWR_UVLO VPWR undervoltage lockout threshold Place 1 V on VPWR and raise the voltage until the CC FETs turn ON 1.9 2.3 2.55 V
VPWR_UVLO_HYS VPWR UVLO hysteresis Place 3 V on VPWR and lower the voltage until the CC FETs turn off. Calculate the difference between the rising and falling UVLO threshold 50 100 200 mV
IVPWR_1S VPWR quiescent current for 1S battery VPWR = 3.3 V, VM = 3.3 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 3.23 7 µA
IVM_1S VM quiescent current for 1S battery VPWR = 3.3 V, VM = 3.3 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 1 µA
IVPWR_1S_Max VPWR quiescent current for 1S battery max VPWR = 4.5 V, VM = 4.5 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 12 µA
IVM_1S_Max VM quiescent current for 1S battery max VPWR = 4.5 V, VM = 4.5 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 1 µA
IVPWR_3S VPWR quiescent current for 3S battery VPWR = 3.6 V, VM = 13.5 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 8 µA
IVM_3S VM quiescent current for 3S battery VPWR = 3.6 V, VM = 13.5 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 3.5 µA
IVPWR_4S VPWR quiescent current for 4S battery VPWR = 3.6 V, VM = 18 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 8 µA
IVM_4S VM quiescent current for 4S battery VPWR = 3.6 V, VM = 18 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 4.5 µA
ICC_LEAK Leakage current for CC pins when device is powered VPWR = 3.3 V, VM = 3.3 V, VC_CCx = 3.6 V, CCx pins are floating, measure leakage into C_CCx pins. Result must be same if CCx side is biased and C_CCx is left floating 5 µA
IC_CC_LEAK_OVP Leakage current for C_CCx pins when device is in OVP VPWR = VM = 0 V or 3.3 V, VC_CCx = 24 V, CCx = 0 V, measure leakage into C_CCx pins 1500 µA
ICC_LEAK_OVP Leakage current for CCx pins when device is in OVP VPWR = VM = 0 V or 3.3 V, VC_CCx = 24 V, CCx = 0 V, measure leakage flowing out of CCx pins 40 µA
FLT PIN
VOL Low-level output voltage for FLT pin IOL = 3 mA. Measure the voltage at the FLT pin 0.4 V

6.7 Timing Requirements

MIN NOM MAX UNIT
POWER-ON AND POWER-OFF TIMINGS
tON Time from crossing rising VPWR UVLO until CC OVP FETs are on. VPWR slew rate = 0.347 V/µs 200 µs
dVPWR_OFF/dt Minimum slew rate allowed to guarantee CC FETs turn off during a power off –0.5 V/µs
OVERVOLTAGE PROTECTION
tOVP_RESPONSE_CC OVP response time on the CC pins. Time from OVP asserted until OVP FETs turn off. Hot-Plug C_CCx to 24 V with a 1-m cable. C_CCx slew rate = 4 V/ns. Place a 30-Ω on CCx 145 ns
tOVP_RECOVERY_CC OVP recovery time on the CC pins. Time from OVP removal until FET turns back on.VM = 10.8 V. Step C_CCx down from 6.3 V to 3.3 V at a 0.343-V/µs slew rate 30 µs
tOVP_RECOVERY_CC OVP recovery time on the CC pins. Time from OVP removal until FET turns back on.VM = 3.3 V. Step C_CCx down from 6.3 V to 0.49 V at a 0.321-V/µs slew rate 200 µs
tOVP_FLT_ASSERTION Time from OVP asserted to FLT assertion.FLT assertion is when the FLT pin reaches 10% of its starting value. C_CCx from 0 V to 6.3 V at a 0.645-V/µs slew rate 1 µs
tOVP_FLT_DEASSERTION Time from OVP removal to FLT deassertion. FLT deassertion is when the FLT pin reaches 90% of its final value. C_CCx from 6.3 V to 0 V at a 0.696-V/µs slew rate 20 µs

6.8 Typical Characteristics

TPD2S300 D025_SLVSDL1.gif
Figure 1. CC S21 BW
TPD2S300 D012_SLVSDL1.gif
Figure 3. CC Short-to-VBUS 20-V VM = 13 V
TPD2S300 D003_SLVSDL1.gif
Figure 5. CC RON Flatness, VM = 8.7 V
TPD2S300 D017_SLVSDL1.gif
Figure 7. CC RON Flatness, VM = 2.7 V
TPD2S300 D001_SLVSDL1.gif
Figure 9. CC IEC 61000-4-2 8-kV Response Waveform
TPD2S300 D004_SLVSDL1.gif
Figure 11. CC Path Leakage Current vs Ambient Temperature at C_CC = 5.5 V
TPD2S300 D020_SLVSDL1.gif
Figure 13. CC OVP Leakage Current vs Ambient Temperature at C_CC = 24 V
TPD2S300 D005_SLVSDL1.gif
Figure 15. C_CC TLP Curve Unpowered
TPD2S300 D021_SLVSDL1.gif
Figure 17. CC IV Curve
TPD2S300 D010_SLVSDL1.gif
Figure 19. VM Supply Leakage vs Ambient Temperature With C_CC Floating or GND
TPD2S300 D011_SLVSDL1.gif
Figure 2. CC Short-to-VBUS 20-V VM = 3.3 V
TPD2S300 D013_SLVSDL1.gif
Figure 4. CC OVP Recovery VM = 3.3 V
TPD2S300 D016_SLVSDL1.gif
Figure 6. CC RON Flatness, VM = 2.7 V
TPD2S300 D018_SLVSDL1.gif
Figure 8. CC RON Flatness, VM = 2.7 V
TPD2S300 D002_SLVSDL1.gif
Figure 10. CC IEC 61000-4-2 –8-kV Response Waveform
TPD2S300 D019_SLVSDL1.gif
Figure 12. C_CC OVP Leakage Current vs Ambient Temperature at C_CC = 24 V
TPD2S300 D007_SLVSDL1.gif
Figure 14. CC FET Turnon Timing
TPD2S300 D006_SLVSDL1.gif
Figure 16. CC TLP Curve Unpowered
TPD2S300 D009_SLVSDL1.gif
Figure 18. VPWR Supply Leakage vs Ambient Temperature With C_CC Floating or GND