SLLS683F JULY   2006  – October 2015 TPD3E001

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRS|6
  • DRL|5
  • DRY|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC –0.3 7 V
VI/O IO voltage tolerance –0.3 VCC + 0.3 V
TJ Junction temperature 150 °C
Lead temperature (soldering, 10 s) 300 °C
Peak pulse power (tp = 8/20 µs) 90 W
Peak pulse power (tp = 8/20 µs) 5.5 A
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±15000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
IEC 61000-4-2 Contact Discharge ±8000
IEC 61000-4-2 Air-gap Discharge ±15000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Operating Voltage VCC Pin 0.9 5.5 V
IOx Pin 0 VCC
Operating free-air temperature, TA -40 85 °C

6.4 Thermal Information

THERMAL METRIC(1) TPD3E001 UNIT
DRL (SOT) DRS (WSON) DRY (USON)
5 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 266.3 91.9 374.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 111.5 106.9 223.4 °C/W
RθJB Junction-to-board thermal resistance 84.5 64.8 227.8 °C/W
ψJT Junction-to-top characterization parameter 16.0 10.2 52.9 °C/W
ψJB Junction-to-board characterization parameter 84.0 64.9 224.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 29.9 87.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VCC = 5 V ± 10%, TA = -40°c to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VCC Supply voltage 0.9 5.5 V
ICC Supply current 1 100 nA
VF Diode forward voltage IF = 10 mA 0.65 0.95 V
VBR Breakdown Voltage IBR = 10mA 11 V
VC Channel clamp voltage(2) TA = 25°C, ±15-kV HBM,
IF = 10 A		 Positive transients VCC + 25 V
Negative transients –25
TA = 25°C,
±8-kV Contact Discharge
(IEC 61000-4-2), IF = 24 A		 Positive transients VCC + 60
Negative transients –60
TA = 25°C,
±15-kV Air-Gap Discharge
(IEC 61000-4-2), IF = 45 A		 Positive transients VCC + 100
Negative transients –100
Ii/o Channel leakage current Vi/o = GND or VCC ±1 nA
Cio Channel input capacitance VCC = 5 V, bias of VCC/2 1.5 pF
Rdyn Dynamic resistance Ii/o = 1 A, between IO pin and ground 1.2 Ω
(1) Typical values are at VCC = 5 V and TA = 25°C.
(2) Channel clamp voltage is not production tested.

6.6 Typical Characteristics

TPD3E001 iocap_iovolt_lls682.gif
VCC = 5.0 V
Figure 1. IO Capacitance vs IO Voltage
TPD3E001 leak_ta_lls682.gif
VCC = 5.5 V
Figure 2. IO Leakage Current vs Temperature