SLVSAM5A January   2011  – April 2016 TPD3F303

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6  Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - Surge Protection
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bidirectional EMI Filtering and Line Termination With Integrated ESD Protection
      2. 7.3.2 IEC 61000-4-2 ESD Protection
      3. 7.3.3 DC Breakdown Voltage
      4. 7.3.4 Low Leakage Current
      5. 7.3.5 Low Noise C-R-C Filter Topology
      6. 7.3.6 Integrated VCC Clamp
      7. 7.3.7 Space-Saving Packages
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Required ESD Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
I/O voltage tolerance I/O pins 5.5 V
TA Operating free-air temperature –40 85 °C
Tstg Storage temperature –55 155 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±15000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings – Surge Protection

VALUE UNIT
V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±15000 V
IEC 61000-4-2 air-gap discharge ±15000

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIO Input pin voltage 0 5.5 V
TA Operating free-air temperature –40 85 °C

6.5 Thermal Information

THERMAL METRIC(1) TPD3F303 UNIT
DPV (USON) DQD (WSON)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 90 92.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 93.4 103.3 °C/W
RθJB Junction-to-board thermal resistance 41.1 36 °C/W
ψJT Junction-to-top characterization parameter 7.9 6.5 °C/W
ψJB Junction-to-board characterization parameter 41 35.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 15.6 16.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vclamp Clamp voltage II/O = ±2 A I/O pin to ground ±10 V
II Leakage current RPU = Open I/O pin to ground 0.1 µA
RCLK CLK series resistors 40 47 55 Ω
RDAT_RST Data/RST series resistors 85 100 115 Ω
CTotal IO Capacitance VI/O = 0 V I/O Pins to GND 16 20 24 pF
VBR Break-down Voltage II/O = 1 mA 6 V
F–3dB –3-dB BW for DATA/RESET line ZSOURCE = 50 Ω
ZLOAD = 50 Ω		 294 MHz
F–3dB –3-dB BW for CLK line ZSOURCE = 50 Ω
ZLOAD = 50 Ω		 308 MHz

6.7 Typical Characteristics

TPD3F303 Iio_ta_lvsam5.gif
VIO = 2.5 V
Figure 1. IIO vs Temperature
TPD3F303 loss_f_lvsam5.gif
Figure 3. Frequency Response Data (0-V Bias)
TPD3F303 cap_vbias_lvsam5.gif
TA = 25°C
Figure 5. Capacitance vs VBIAS
TPD3F303 Iio_Vio_lvsam5.gif
Figure 2. IIO vs VIO
TPD3F303 xtalk_sm_lvsam5.gif
Figure 4. Channel-to-Channel Crosstalk