SLUSDH1B may   2020  – april 2023 TPD3S713-Q1 , TPD3S713A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 FAULT Response
      2. 8.3.2 Cable Compensation
        1. 8.3.2.1 Design Procedure
      3. 8.3.3 DP and DM Protection
      4. 8.3.4 VBUS OVP Protection
      5. 8.3.5 Output and DP or DM Discharge
      6. 8.3.6 Overcurrent Protection
      7. 8.3.7 Undervoltage Lockout
      8. 8.3.8 Thermal Sensing
      9. 8.3.9 Current-Limit Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Truth Table (TT)
      2. 8.4.2 Client Mode
      3. 8.4.3 High-Bandwidth Data-Line Switch
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitance
        2. 9.2.2.2 Output Capacitance
        3. 9.2.2.3 BIAS Capacitance
        4. 9.2.2.4 Output and BIAS TVS
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RVC|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.3 Application Curves

GUID-33A42A32-B024-4CBD-A2CD-8F9D6D5721E7-low.png
VBAT = 16 V t = 5 µs/div
Figure 9-2 Disabled, 25-V, 1206, X7R COUT Capacitor Without SMAJ16
GUID-E42D04FE-B3AF-4A76-B500-598D002B6999-low.png
t = 20 µs/div
Figure 9-4 Disabled, 25-V, 1206, X7R COUT Capacitor With SMAJ16, BUS Shorted to Battery
GUID-47044A2A-DA34-4321-8EC7-9D86C86A5872-low.png
t = 20 µs/div
Figure 9-6 DC-DC VIN Floating, BUS Shorted to Battery
GUID-47469AE4-7E8F-47C2-BC81-59FC233BA884-low.png
RBIAS = 5.1 kΩ t = 2 µs/div
Figure 9-8 Disabled, DP_IN Shorted to Battery
GUID-B7AE7E68-4CF2-4D9E-AD78-C1C355AE8823-low.png
R(BIAS) = 5.1 kΩ t = 2 µs/div R(DP_OUT) = 15 kΩ
Figure 9-10 Enabled, DP_IN Shorted to Battery
GUID-B5E4A688-C02E-42F7-BD96-A02D0CE52F2A-low.png
VBAT = 18 V t = 5 µs/div
Figure 9-3 Disabled, 35-V, 1210, X7R COUT Capacitor Without SMAJ18
GUID-74D09E01-F610-4923-AF59-B40A61B798C4-low.png
t = 20 µs/div
Figure 9-5 Disabled, 35-V, 1210, X7R COUT Capacitor With SMAJ18, BUS Shorted to Battery
GUID-4BAFDE31-36FC-4C83-B351-B9574799E046-low.png
t = 20 µs/div
Figure 9-7 Enable BUS Shorted to Battery
GUID-101A4F18-8362-49BA-92BF-C019478B76AF-low.png
RBIAS = 5.1 kΩ t = 2 µs/div
Figure 9-9 DC-DC VIN Floating, DP_IN Shorted to Battery