SLUSDH1B may   2020  – april 2023 TPD3S713-Q1 , TPD3S713A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 FAULT Response
      2. 8.3.2 Cable Compensation
        1. 8.3.2.1 Design Procedure
      3. 8.3.3 DP and DM Protection
      4. 8.3.4 VBUS OVP Protection
      5. 8.3.5 Output and DP or DM Discharge
      6. 8.3.6 Overcurrent Protection
      7. 8.3.7 Undervoltage Lockout
      8. 8.3.8 Thermal Sensing
      9. 8.3.9 Current-Limit Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Truth Table (TT)
      2. 8.4.2 Client Mode
      3. 8.4.3 High-Bandwidth Data-Line Switch
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitance
        2. 9.2.2.2 Output Capacitance
        3. 9.2.2.3 BIAS Capacitance
        4. 9.2.2.4 Output and BIAS TVS
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RVC|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

Unless otherwise noted, –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 5.5 V, V(EN) = V(INT1) = V(ILIM_SEL) = V(IN), V(INT2) = GND, R(FAULT) = 10 kΩ, R(IMON) = 2.55 kΩ, R(ILIM_HI) = 52.3 kΩ. Positive currents are into pins. Typical values are at TJ = 25°C. All voltages are with respect to GND.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
trBUS voltage rise timeV(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω1.051.753.1ms
tfBUS voltage fall time0.270.470.82ms
tonBUS voltage turn-on timeV(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω7.511ms
toffBUS voltage turn-off time2.75ms
t(DCHG_S)Discharge hold time (ILIM_SEL change)Time V(OUT) < 0.7V1.122.9s
t(IOS)BUS short-circuit response time(1)V(IN) = 5 V, R(SHORT) = 50 mΩ2µs
t(OC_BUS_FAULT)BUS FAULT deglitch timeBidirectional deglitch applicable to current-limit condition only (no deglitch assertion for OTSD)5.58.511.5ms
tpdAnalog switch propagation delay (1)V(IN) = 5 V0.14ns
t(SK)Analog switch skew between opposite transitions of the same port (tPHL – tPLH) (1)V(IN) = 5 V0.02ns
t(OV_Data)DP_IN and DM_IN overvoltage protection response time5µs
t(OV_BUS)BUS overvoltage protection response time0.3µs
t(OV_Data_FAULT)DP_IN and DM_IN FAULT-asserted degltich time111623ms
BUS FAULT-asserted degltich time111623ms
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.