SLVSEL8 June   2018 TPD6S300A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     CC and SBU Over-Voltage Protection
    2.     CC and DP/DM Over-Voltage Protection
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings—JEDEC Specification
    3. 7.3 ESD Ratings—IEC Specification
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 24-VDC Tolerant
      2. 8.3.2 6-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2, DP, DM Pins)
      3. 8.3.3 CC1, CC2 Overvoltage Protection FETs 600 mA Capable for Passing VCONN Power
      4. 8.3.4 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
      5. 8.3.5 Advantages over TPD6S300
        1. 8.3.5.1 Improved Dead Battery Performance
        2. 8.3.5.2 USB Type-C Port Stays Connected during an IEC 61000-4-2 ESD Strike
      6. 8.3.6 3-mm × 3-mm WQFN Package
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VBIAS Capacitor Selection
        2. 9.2.2.2 Dead Battery Operation
        3. 9.2.2.3 CC Line Capacitance
        4. 9.2.2.4 Additional ESD Protection on CC and SBU Lines
        5. 9.2.2.5 FLT Pin Operation
        6. 9.2.2.6 How to Connect Unused Pins
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Thermal Information

THERMAL METRIC(1)
TPD6S300A
UNIT
RUK (WQFN)
20 PINS
RθJA Junction-to-ambient thermal resistance 45.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 48.8 °C/W
RθJB Junction-to-board thermal resistance 17.1 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 17.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.