SLIS182 November 2016 TPL0401A-10-Q1 , TPL0401B-10-Q1
PRODUCTION DATA.
Protection diodes limit the voltage compliance at SDA, SCL, terminal H, and terminal W, making it important to power up VDD first before applying any voltage to SDA, SCL, terminal H, and terminal W. The diodes are forward-biasing, meaning VDD can be powered unintentionally if VDD is not powered first. The ideal power-up sequence is VDD, digital inputs, and VW and VH. The order of powering digital inputs, VH and VW does not matter as long as they are powered after VDD.
In the event of a glitch or data corruption, the TPL0401-10-Q1 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
Table 4 specifies the performance of the power-on reset feature for the TPL0401-10-Q1 for both types of power-on reset.
In order to ensure a complete device reset after a power up condition, the user must wait 120 µs after power up before initiating communication with the TPL0401x-10-Q1. See Figure 23 for an example waveform.
When DPOT is powered off, the impedance of the device is undefined and not known.
Upon power-up, the device returns to 0×40h code because this device does not contain non-volatile memory.