SCPS295 September   2024 TPLD801

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT macro-cell
        2. 7.3.3.2 3-Bit LUT macro-cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop/Latch macro-cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch with Set/Reset macro-cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay macro-cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter/Delay macro-cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell
      6. 7.3.6 Selectable Frequency Oscillator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 One-Time Programmable Memory (OTP)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Option Addendum
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER VCC MIN TYP MAX UNIT
Digital IO
tpd Delay Digital input without Schmitt trigger to Push-pull output - Rising 1.8V ± 0.15V 46.9 ns
Digital input without Schmitt trigger to Push-pull output - Falling 39.5
Digital input without Schmitt trigger to Push-pull output - Rising 3.3V ± 0.3V 27.3
Digital input without Schmitt trigger to Push-pull output - Falling 26.4
Digital input without Schmitt trigger to Push-pull output - Rising 5V ± 0.5V 22.3
Digital input without Schmitt trigger to Push-pull output - Falling 22.5
tpd Delay Digital input with Schmitt trigger to Push-pull output - Rising 1.8V ± 0.15V 50.8 ns
Digital input with Schmitt trigger to Push-pull output - Falling 42.2
Digital input with Schmitt trigger to Push-pull output - Rising 3.3V ± 0.3V 29.7
Digital input with Schmitt trigger to Push-pull output - Falling 27.2
Digital input with Schmitt trigger to Push-pull output - Rising 5V ± 0.5V 24.2
Digital input with Schmitt trigger to Push-pull output - Falling 22.8
tpd Delay Low-voltage digital input to Push-pull output - Rising 1.8V ± 0.15V 45.6 ns
Low-voltage digital input to Push-pull output - Falling 49.5
Low-voltage digital input to Push-pull output - Rising 3.3V ± 0.3V 25.4
Low-voltage digital input to Push-pull output - Falling 33.0
Low-voltage digital input to Push-pull output - Rising 5V ± 0.5V 19.6
Low-voltage digital input to Push-pull output - Falling 31.5
tpd Delay Digital input without Schmitt trigger to Open-drain NMOS output - Rising 1.8V ± 0.15V 57.0 ns
Digital input without Schmitt trigger to Open-drain NMOS output - Falling 39.3
Digital input without Schmitt trigger to Open-drain NMOS output - Rising 3.3V ± 0.3V 47.8
Digital input without Schmitt trigger to Open-drain NMOS output - Falling 26.2
Digital input without Schmitt trigger to Open-drain NMOS output - Rising 5V ± 0.5V 38.2
Digital input without Schmitt trigger to Open-drain NMOS output - Falling 22.3
tpd Delay Output enable from pin, OE, Hi-Z to 1 - Rising 1.8V ± 0.15V 45.9 ns
3.3V ± 0.3V 27.3
5V ± 0.5V 22.4
tpd Delay Output enable from pin, OE, Hi-Z to 0 - Falling 1.8V ± 0.15V 41.1 ns
3.3V ± 0.3V 24.5
5V ± 0.5V 19.6
Configurable Use Logic
tpd Delay 2-bit LUT - Rising 1.8V ± 0.15V 1.16 ns
2-bit LUT - Falling 1.31
2-bit LUT - Rising 3.3V ± 0.3V 1.16
2-bit LUT - Falling 1.31
2-bit LUT - Rising 5V ± 0.5V 1.16
2-bit LUT - Falling 1.31
tpd Delay 3-bit LUT - Rising 1.8V ± 0.15V 1.04 ns
3-bit LUT - Falling 1.26
3-bit LUT - Rising 3.3V ± 0.3V 1.04
3-bit LUT - Falling 1.26
3-bit LUT - Rising 5V ± 0.5V 1.04
3-bit LUT - Falling 1.26
tpd Delay 4-bit LUT - Rising 1.8V ± 0.15V 1.62 ns
4-bit LUT - Falling 1.99
4-bit LUT - Rising 3.3V ± 0.3V 1.62
4-bit LUT - Falling 1.99
4-bit LUT - Rising 5V ± 0.5V 1.62
4-bit LUT - Falling 1.99
tpd Delay Latch - Rising 1.8V ± 0.15V 1.32 ns
Latch - Falling 1.34
Latch - Rising 3.3V ± 0.3V 1.32
Latch - Falling 1.34
Latch - Rising 5V ± 0.5V 1.32
Latch - Falling 1.34
tpd Delay Latch nRST/nSET - Rising 1.8V ± 0.15V 1.43 ns
Latch nRST/nSET - Falling 1.46
Latch nRST/nSET - Rising 3.3V ± 0.3V 1.43
Latch nRST/nSET - Falling 1.46
Latch nRST/nSET - Rising 5V ± 0.5V 1.43
Latch nRST/nSET - Falling 1.46
Counter/Delay
tpd Delay CNT/DLY - Rising 1.8V ± 0.15V 2.61 ns
CNT/DLY - Falling  2.59
CNT/DLY - Rising 3.3V ± 0.3V 2.61
CNT/DLY - Falling  2.59
CNT/DLY - Rising 5V ± 0.5V 2.61
CNT/DLY - Falling  2.59
Oscillator
ferr Oscillator frequency error OSC0 25 kHz 1.8V ± 0.15V -5 5 %
3.3V ± 0.3V -5 5
5V ± 0.5V -5 5
ferr Oscillator frequency error OSC0 2 MHz 1.8V ± 0.15V -5 5 %
3.3V ± 0.3V -5 5
5V ± 0.5V -5 5
td_osc Oscillator startup delay OSC0 25 kHz (Auto power on) 1.8V ± 0.15V 14.3 µs
3.3V ± 0.3V 14.2
5V ± 0.5V 14.1
td_osc Oscillator startup delay OSC0 2 MHz (Auto power on) 1.8V ± 0.15V 6.24 µs
3.3V ± 0.3V 6.43
5V ± 0.5V 6.64
tset_osc Oscillator startup settling time OSC0 25 kHz (Auto power on) 1.8V ± 0.15V 1 µs
3.3V ± 0.3V 1
5V ± 0.5V 1
tset_osc Oscillator startup settling time OSC0 2 MHz (Auto power on) 1.8V ± 0.15V 7 µs
3.3V ± 0.3V 7
5V ± 0.5V 7
td_err Delay error OSC (Forced power on) 1.65V to 5.5V 0 1 CLK cycle
Programmable Filter
tpflt_pw Pulse width, 1 cell PFLT mode: (any) edge detect, edge detect output 1.8V ± 0.15V 138.0 ns
3.3V ± 0.3V 141.3
5V ± 0.5V 141.7
tpflt_pw Pulse width, 2 cells PFLT mode: (any) edge detect, edge detect output 1.8V ± 0.15V 232.6 ns
3.3V ± 0.3V 236.0
5V ± 0.5V 236.5
tpflt_pw Pulse width, 3 cells PFLT mode: (any) edge detect, edge detect output 1.8V ± 0.15V 326.8 ns
3.3V ± 0.3V 330.5
5V ± 0.5V 330.9
tpflt_pw Pulse width, 4 cells PFLT mode: (any) edge detect, edge detect output 1.8V ± 0.15V 420.9 ns
3.3V ± 0.3V 424.7
5V ± 0.5V 425.0
tpflt_pd
 Delay, any cells PFLT mode: (any) edge detect, edge detect output 1.8V ± 0.15V 67.4 ns
3.3V ± 0.3V 48.7
5V ± 0.5V 43.7
tpflt_d Delay, 1 cell PFLT mode: both edge delay (shared macrocell inputs) 1.8V ± 0.15V 208.4 ns
3.3V ± 0.3V 191.5
5V ± 0.5V 186.9
tpflt_d Delay, 2 cells PFLT mode: both edge delay (shared macrocell inputs) 1.8V ± 0.15V 303.3 ns
3.3V ± 0.3V 286.3
5V ± 0.5V 281.5
tpflt_d Delay, 3 cells PFLT mode: both edge delay (shared macrocell inputs) 1.8V ± 0.15V 397.7 ns
3.3V ± 0.3V 380.6
5V ± 0.5V 375.9
tpflt_d Delay, 4 cells PFLT mode: both edge delay (shared macrocell inputs) 1.8V ± 0.15V 491.9 ns
3.3V ± 0.3V 474.6
5V ± 0.5V 469.8