SLUSEZ3A December   2023  – December 2024 TPS1200-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving Using FET Gate (PU, PD) Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Overvoltage (OV) and Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 7.3.7 TPS12000-Q1 as a Simple Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Driving Power at all Times (PAAT) Loads
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3.2 Short-Circuit Protection With Latch-Off

Connect an approximately 100kΩ resistor across CTMR as shown in . With this resistor, during the charging cycle, the voltage across CTMR gets clamped to a level below V(TMR_SC) resulting in a latch-off behavior and FLT asserts low at same time.

Use Equation 8 to calculate CTMR capacitor to be connected between TMR and GND for RTMR = 100kΩ.

Equation 8. CTMR=tSCRTMR × ln11-1.1RTMR ×80 µA

Where,

ITMR is internal pull-up current of 80μA.

tSC is desired short-circuit response time.

Toggle INP or EN/UVLO (below V(ENF)) or power cycle VS below V(VS_PORF) to reset the latch. At low edge, the timer counter is reset and CTMR is discharged. PU pulls up to BST when INP is pulled high.

TPS1200-Q1 Short-Circuit Protection With Latch-OffFigure 7-10 Short-Circuit Protection With Latch-Off