SLUSEZ3A December   2023  – December 2024 TPS1200-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving Using FET Gate (PU, PD) Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Overvoltage (OV) and Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 7.3.7 TPS12000-Q1 as a Simple Gate Driver
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Driving Power at all Times (PAAT) Loads
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

TJ = –40 ℃ to +125℃. V(VS) = 12 V, V(BST – SRC) = 11 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VS Operating input voltage 3.5 40 V
V(S_PORR) Input supply  POR threshold, rising 1.78 2.5 3.27 V
V(S_PORF) Input supply POR threshold, falling 1.71 2.36 3.1 V
Total System Quiescent current, I(GND) V(EN/UVLO) = 2 V 46 55 µA
Total System Quiescent current, I(GND)   V(EN/UVLO) =  2 V, –40°C ≤ TJ ≤ +85°C 53 µA
I(SHDN) SHDN current, I(GND) V(EN/UVLO) = 0 V, V(SRC) = 0 V 0.75 3.3 µA
I(REV) I(VS) leakage current during Reverse Polarity  V(VS) = – 40 V 11 13 23 µA
ENABLE, UNDERVOLTAGE LOCKOUT (EN/UVLO), SHORT CIRCUIT COMPARATOR TEST (SCP_TEST) INPUT
V(UVLOR) UVLO threshold voltage, rising 1.176 1.23 1.287 V
V(UVLOF) UVLO threshold voltage, falling 1.09 1.136 1.184 V
V(ENR) Enable threshold voltage for low Iq shutdown, rising 1 V
V(ENF) Enable threshold voltage for low Iq shutdown, falling 0.3 V
I(EN/UVLO) Enable input leakage current V(EN/UVLO)  = 12 V 180 310 nA
V(SCP_TEST_H) SCP test mode rising threshold 2 V
V(SCP_TEST_L) SCP test mode falling threshold 0.8 V
I(SCP_TEST) SCP_TEST input leakage current 90 700 nA
OVER VOLTAGE PROTECTION (OV) INPUT 
V(OVR) Overvoltage threshold input, risIng 1.171 1.225 1.278 V
V(OVF) Overvoltage threshold input, falling 1.088 1.138 1.186 V
I(OV) OV Input leakage current 86 200 nA
CHARGE PUMP (BST–SRC)
I(BST) Charge Pump Supply current V(BST – SRC)  = 10 V, V(EN/UVLO) =  2 V 190 345 466 µA
V(BST_UVLOR) V(BST – SRC) UVLO voltage threshold, rising V(EN/UVLO) = 2 V 8.1 9 9.9 V
V(BST_UVLOF) V(BST – SRC) UVLO voltage threshold, falling V(EN/UVLO) = 2 V 7.28 8.2 8.9 V
V(BST–SRC_ON) Charge Pump Turn ON voltage V(EN/UVLO) = 2 V 9.3 10.3 11.4 V
V(BST–SRC_OFF) Charge Pump Turn OFF voltage V(EN/UVLO) = 2 V 10.4 11.6 12.8 V
V(BST–SRC) Charge Pump Voltage at V(VS) = 3.5 V V(EN/UVLO) = 2 V 9.1 10.5 11.62 V
GATE DRIVER OUTPUTS (G1PU, G1PD)
I(PU) Peak Source Current 1.69 A
I(PD) Peak Sink Current 2 A
V(G_GOOD) VGS good threshold 5.5 7 8.3 V
SHORT CIRCUIT PROTECTION (ISCP)
ISCP SCP Input Bias current 8.4 10 12.33 µA
V(SCP) SCP threshold R(ISCP) =  140.5 kΩ 300 mV
R(ISCP) =  28 kΩ 60 75 90 mV
R(ISCP) =  10.5 kΩ 32 40 48 mV
R(ISCP) =  500 Ω 15 20 25 mV
R(ISCP) =  Open 757 mV
V(SCP) SCP threshold with external bias on ISCP pin V(ISCP) = 1.405 V 283 300 315 mV
V(ISCP) = 280 mV 67.8 75 81.7 mV
V(ISCP) = 105 mV 33.3 40 46.2 mV
DELAY TIMER (TMR)
I(TMR_SRC_CB) TMR source current 67 87 104 µA
I(TMR_SRC_FLT) TMR source current  1.4 2.73 3.8 µA
I(TMR_SNK) TMR sink  current 2.17 2.8 3.4 µA
V(TMR_SC) 0.93 1.1 1.2 V
V(TMR_LOW) 0.15 0.21 0.25 V
N(A-R Count) 32
INPUT CONTROL (INP), FAULT FLAGS (FLT, FLT_GD)
R(FLT),  R(FLT_GD) FLT, FLT_GD Pull-down resistance 53 85 107
I(FLT),  I(FLT_GD) FLT, FLT_GD Input leakage current 0 V ≤ V(FLT) ≤ 20 V 410 nA
V(INP_H) 2 V
V(INP_L) 0.8 V
I(INP) INP Input leakage current 89 206 nA
V(CS_SEL_H)  CS_SEL threshold for low side sensing 1.35 2 V
V(CS_SEL_L)  CS_SEL threshold for high side sensing 0.8 1.36 V
I(CS_SEL) CS_SEL Input leakage current 10 88.8 200 nA