SLUSF08A March   2024  – September 2024 TPS1213-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving
        1. 7.3.2.1 Using Low Power Bypass FET (G2 drive) for Load Capacitor Charging
        2. 7.3.2.2 Using Main FET (G1 Drive) Gate Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 State Transition Timing Diagram
      3. 7.4.3 Power Down
      4. 7.4.4 Shutdown Mode
      5. 7.4.5 Low Power Mode
      6. 7.4.6 Active Mode
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application 1: Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application 2: Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
      1. 8.3.1 Design Requirements
      2. 8.3.2 External Component Selection
      3. 8.3.3 Application Curves
    4. 8.4 TIDA-020065: Automotive Smart Fuse Reference Design Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup, Output Bulk Capacitor Charging, Bi-directional Current Sensing and Software I2t
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGX|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Design Procedure

Selection of MOSFET, Q1 and Q2

For selecting the MOSFET Q1 and Q2, important electrical parameters are the maximum continuous drain current ID, the maximum drain-to-source voltage VDS(MAX), the maximum drain-to-source voltage VGS(MAX), and the drain-to-source ON resistance RDSON.

The maximum continuous drain current, ID, rating must exceed the maximum continuous load current.

The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest voltage seen in the application. Considering 35V as the maximum application voltage due to load dump, MOSFETs with VDS voltage rating of 40V is chosen for this application.

The maximum VGS TPS12130-Q1 can drive is 11V, so a MOSFET with 15V minimum VGS rating must be selected.

To reduce the MOSFET conduction losses, an appropriate RDS(ON) is preferred.

Based on the design requirements, two of BUK7J1R4-40H are selected and its ratings are:

  • 40V VDS(MAX) and ±20V VGS(MAX)
  • RDS(ON) is 1.06mΩ typical at 10- VGS
  • MOSFET Qg(total) is 73nC typical

TI recommends to make sure that the short-circuit conditions such max VIN and ISC are within SOA of selected FETs (Q1 and Q2) for > tSC timing.

Selection of Bootstrap Capacitor, CBST

The internal charge pump charges the external bootstrap capacitor (connected between BST and SRC pins) with approximately 345μA. Use the following equation to calculate the minimum required value of the bootstrap capacitor for driving two parallel BUK7J1R4-40H MOSFETs

Equation 12. CBST = Qg(total)1 V = 2 ×73 nF = 146 nF

Choose closest available standard value: 150nF, 10%.

Programming the Short-Circuit Protection Threshold – RISCP Selection

The RISCP sets the short-circuit protection threshold, whose value can be calculated using following equation:

Equation 13. RISCP () = ISC × RSNS - 19 mV2 µA

To set 100A as short-circuit protection threshold, RISCP value is calculated to be 15.5kΩ for two FETs in parallel.

Choose the closest available standard value: 15.6kΩ, 1%.

Programming the Fault timer Period – CTMR Selection

For the design example under discussion, overcurrent transients are allowed for 50μs duration. This blanking interval, tSC (or circuit breaker interval, TCB) can be set by selecting appropriate capacitor CTMR from TMR pin to ground. The value of CTMR to set 50μs for tSC can be calculated using following equation:

Equation 14. CTMR=80 μA × tSC1.1

Choose closest available standard value: 3.3nF, 10%.

TMR pin can be left floating for fast response of tSC < 10 μs.

Programming the Load Wakeup Threshold – RBYPASS and Q3 Selection

During normal operation, the resistor RBYPASS along with bypass FET RDSON is used to set load wakeup current threshold.

For selecting the MOSFET Q3, important electrical parameters are the maximum continuous drain current ID, the maximum drain-to-source voltage VDS(MAX), the maximum drain-to-source voltage VGS(MAX), and the drain-to-source ON resistance RDSON.

Based on the design requirements, BUK6D23-40E is selected and its ratings are:

  • 40-V VDS(MAX) and ±20-V VGS(MAX)

  • RDS(ON) is 17-mΩ typical at 10-V VGS

  • MOSFET Qg(total) is 11 nC typical

  • MOSET VGS(th) is 1.3 V min

  • MOSFET CISS is 582 pF typical

The recommended range of the short-circuit threshold voltage which is same as load wakeup threshold, V(SCP/LWU), extends from 30 mV to 500 mV. Values near the low threshold of 30 mV can be affected by the system noise. Values near the upper threshold of 500 mV would result in high short-circuit current threshold. To minimize both the concerns, 50 mV is selected as the short-circuit or load wakeup threshold voltage.

The V(SCP/LWU) value can also be calculated based on selected RISCP resistor by following equation:

Equation 15. V ( S C P / L W U )   ( m V ) =   2   μ A   ×   R I S C P   + 19   m V

RBYPASS resistor value can be selected using below equation:

Equation 16. RBYPASS = V(SCP/LWU)ILWU -RDSON_BYPASS

To set 50 mA as load wakeup threshold, RBYPASS value is calculated to be ~ 1 Ω.

The average power rating of the bypass resistor can be calculated by following equation:

Equation 17. PAVG= ILWU2× RBYPASS

The average power dissipation of RBYPASS is calculated to be ~ 0.0025 W

The peak power dissipation in the bypass resistor is given by following equation:

Equation 18. PPEAK= VBATT_MAX2RBYPASS

The peak power dissipation of RBYPASS is calculated to be ~ 256 W

The peak power dissipation time for power-up with short into LPM can be calculated based on following equation:

Equation 19. TPULSE= CISS× V(G2_GOOD) - VGS(th)I(G2) + 10 µs

where,

V(G2_GOOD) is internal threshold with 7 V (typical) value,

I(G2) is 165 μA (typical),

VGS(th) is gate to source voltage and CISS is effective input capacitance of selected bypass FET.

Based on Equation 28, TPULSE is calculated to be ~ 32 μs.

One 1-Ω, 1.5-W, 1% CRCW25121R00JNEGHP resistor is used to support both average and peak power dissipation for > TPULSE time calculated in Equation 28.

TI suggests the designer to share the entire power dissipation profile of bypass resistor with the resistor manufacturer and get their recommendation.

The peak short-circuit current in bypass path can be calculated based on following equation:

Equation 20. IPEAK_BYPASS=VIN_MAXRBYPASS

IPEAK_BYPASS is calculated to be 16-A based on RBYPASS selected in Equation 25.

Setting the Undervoltage Lockout Set Point, R3 and R4

The undervoltage lockout (UVLO) can be adjusted using an external voltage divider network of R3 and R4 connected between VS, EN/UVLO and GND pins of the device. The values required for setting the undervoltage and overvoltage are calculated by solving below equation:

Equation 21. V(UVLOR)= VINUVLO× R4R3+ R4

For minimizing the input current drawn from the power supply, TI recommends to use higher values of resistance for R3 and R4. However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, I(R34) must be chosen to be 20 times greater than the leakage current of UVLO pin.

From the device electrical specifications, V(UVLOR) = 1.24 V. From the design requirements, VINUVLO is 6.5 V. To solve the equation, first choose the value of R3 = 470 kΩ and use Equation 21 to solve for R4 = 107.5 kΩ.

Choose the closest standard 1% resistor values: R3 = 470 kΩ, and R4 = 107 kΩ.