SLUSF08 March   2024 TPS1213-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving
        1. 7.3.2.1 Using Low Power Bypass FET (G2 drive) for Load Capacitor Charging
        2. 7.3.2.2 Using Main FET's (G1 drive) Gate Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Device Functional Modes
        1. 7.3.4.1 State Diagram
        2. 7.3.4.2 State Transition Timing Diagram
        3. 7.3.4.3 Power Down
        4. 7.3.4.4 Shutdown Mode
        5. 7.3.4.5 Low Power Mode
        6. 7.3.4.6 Active Mode
      5. 7.3.5 Undervoltage Protection (UVLO)
      6. 7.3.6 Reverse Polarity Protection
      7. 7.3.7 Short-Circuit Protection Diagnosis (SCP_TEST)
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Limitations
        1. 8.1.1.1 Short-Circuit Protection Delay
        2. 8.1.1.2 Short-Circuit Protection and Load wakeup Threshold
    2. 8.2 Typical Application 1: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application 2: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
      1. 8.3.1 Design Requirements
      2. 8.3.2 External Component Selection
      3. 8.3.3 Application Curves
    4. 8.4 TIDA-020065: Automotive Smart Fuse Reference Design driving Power at all times (PAAT) Loads With Automatic Load Wakeup, Output Bulk Capacitor Charging, Bi-directional Current Sensing and Software I2t
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGX|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

TJ = –40 ℃ to +125℃. V(VS) = 12 V, V(BST – SRC) = 11 V, V(SRC) = 0 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VS Operating input voltage 3.5 40 V
I(Q) Total System Quiescent current, I(GND) in Active mode V(EN/UVLO) = V(LPM) = 2 V 44 µA
Total System Quiescent current, I(GND) in low power mode V(EN/UVLO) = 2 V, V(LPM) = 0 V 35 µA
I(SHDN) SHDN current, I(GND) V(EN/UVLO) = 0 V, V(SRC) = 0 V 1 µA
ENABLE, UNDERVOLTAGE LOCKOUT (EN/UVLO), SHORT CIRCUIT COMPARATOR TEST (SCP_TEST) INPUT
V(UVLOR) UVLO threshold voltage, rising 1.24 V
V(UVLOF) UVLO threshold voltage, falling 1.14 V
V(ENR) Enable threshold voltage for shutdown, rising 1.02 V
V(ENF) Enable threshold voltage for shutdown, falling 0.3 V
V(SCP_TEST) SCP test mode rising threshold 2 V
V(SCP_TEST) SCP  test mode falling threshold 0.8 V
I(EN/UVLO) Enable input leakage current V(EN/UVLO)  = 12 V 180 nA
CHARGE PUMP (BST–SRC)
V(BST – SRC_ON) Charge Pump Turn ON voltage V(EN/UVLO) = 2 V 10 V
V(BST – SRC_OFF) Charge Pump Turnoff voltage V(EN/UVLO) =  2 V 11.8 V
V(BST_UVLOR) V(BST – SRC) UVLO voltage threshold, rising V(EN/UVLO) = 2 V 9.5 V
V(BST_UVLOF) V(BST – SRC) UVLO voltage threshold, falling V(EN/UVLO) =  2 V 7.2 V
GATE DRIVER OUTPUTS (G1PU, G1PD, G2)
I(G1PU) Peak Source Current 1.69 A
I(G2) G2 Source Current 165 µA
I(G1PD) Peak Sink Current 2 A
I(G2) G2 Peak Sink Current 2 A
V(G1_GOOD) G1 Good rising threshold 7 V
V(G2_GOOD) G2 Good rising threshold 7 V
SHORT CIRCUIT PROTECTION AND LOAD WAKE UP THRESHOLD (ISCP/LWU)
ISCP/LWU SCP/LWU Input Bias current 10 µA
V(SCP/LWU) SCP/LWU threshold R(ISCP) =  32.5 kΩ 60 75 90 mV
R(ISCP) =  15 kΩ 40 mV
DELAY TIMER (TMR)
I(TMR_SRC_CB) TMR source current 80 µA
I(TMR_SRC_FLT) TMR source current  2.2 µA
I(TMR_SNK) TMR sink  current 2.5 µA
V(TMR_SC) 1.1 V
V(TMR_LOW) 0.2 V
N(A-R Count) 32
INPUT CONTROLS (INP, LPM), FAULT (FLT) & WAKE FLAG (WAKE)
R(FLT), R(WAKE) FLT, WAKE switch Pull-down resistance 70 Ω
V(INP_H), V(LPM_H) 2 V
V(INP_L), V(LPM_L) 0.8 V