The TPS20xxC and TPS20xxC-2 power-distribution switch family is intended for applications, such as USB, where heavy capacitive loads and short circuits are likely to be encountered. This family offers multiple devices with fixed current-limit thresholds for applications from 0.5 A to 2 A.
The TPS20xxC and TPS20xxC-2 family limits the output current to a safe level by operating in a constant-current mode when the output load exceeds the current limit threshold. This provides a predictable fault current under all conditions. The fast overload response time eases the burden on the main 5-V supply to provide regulated power when the output is shorted. The power-switch rise and fall times are controlled to minimize current surges during turnon and turnoff.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS20xxC, TPS20xxC-2 |
SOT-23 (5) | 2.90 mm × 1.60 mm |
VSSOP (8) | 3.00 mm × 3.00 mm | |
MSOP-PowerPAD (8) | 3.00 mm × 3.00 mm |
Changes from G Revision (July 2013) to H Revision
Changes from F Revision (August 2012) to G Revision
Changes from E Revision (April 2012) to F Revision
Changes from D Revision (February 2012) to E Revision
Changes from C Revision (October 2011) to D Revision
Changes from B Revision (September 2011) to C Revision
Changes from A Revision (July 2011) to B Revision
Changes from * Revision (June 2011) to A Revision
MAXIMUM OPERATING CURRENT |
OUTPUT DISCHARGE | ENABLE | BASE PART NUMBER | PACKAGED DEVICE AND MARKING(1) | ||
---|---|---|---|---|---|---|
MSOP-8 (DGN) PowerPAD™ |
SOT23-5 (DBV) |
VSSOP-8 (DGK) |
||||
0.5 | Y | Low | TPS2041C | —(2) | PYJI | — |
0.5 | Y | High | TPS2051C | — | VBYQ | — |
1 | Y | Low | TPS2061C | PXMI | PXLI | — |
1 | Y | High | TPS2065C | VCAQ | VCAQ | — |
1 | N | High | TPS2065C-2 | PYRI | PYQI | — |
1.5 | Y | Low | TPS2068C | PXNI | — | — |
1.5 | Y | High | TPS2069C | VBUQ | PYKI | — |
1.5 | N | High | TPS2069C-2 | PYSI | — | — |
2 | Y | Low | TPS2000C | BCMS | — | PXFI |
2 | Y | High | TPS2001C | VBWQ | – | PXGI |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN/EN | 4 | I | Enable input, logic high turns on power switch |
FLT | 5 | O | Active-low open-drain output, asserted during overcurrent, or overtemperature conditions |
GND | 1 | — | Ground connection |
IN | 2, 3 | PWR | Input voltage and power-switch drain; connect a 0.1-µF or greater ceramic capacitor from IN to GND close to the IC |
OUT | 6, 7, 8 | PWR | Power-switch output, connect to load |
PowerPAD (DGN Only) | PowerPAD | — | Internally connected to GND. Connect PAD to GND plane as a heatsink for the best thermal performance. PAD may be left floating if desired. See Power Dissipation and Junction Temperature for guidance. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage on IN, OUT, EN or EN, FLT (4) | –0.3 | 6 | V | |
Voltage from IN to OUT | –6 | 6 | V | |
Maximum junction temperature, TJ | Internally Limited | |||
Storage temperature, Tstg | –60 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | |||
IEC 61000-4-2 contact discharge | ±8000 | |||
IEC 61000-4-2 air-gap discharge(3) | ±15000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VIN | Input voltage, IN | 4.5 | 5.5 | V | ||
VEN | Input voltage, EN or EN | 0 | 5.5 | V | ||
VIH | High-level input voltage, EN or EN | 2 | V | |||
VIL | Low-level input voltage, EN or EN | 0.7 | V | |||
IOUT | Continuous output current, OUT(1) | TPS2041C and TPS2051C | 0.5 | A | ||
TPS2061C, TPS2065C and TPS2065C-2 | 1 | |||||
TPS2068C, TPS2069C and TPS2069C-2 | 1.5 | |||||
TPS2000C and TPS2001C | 2 | |||||
TJ | Operating junction temperature | –40 | 125 | °C | ||
IFLT | Sink current into FLT | 0 | 5 | mA |
THERMAL METRIC(1) | TPS20xxC, TPS20xxC-2 | UNIT | ||
---|---|---|---|---|
DBV (SOT-23)(2) | DBV (SOT-23)(3) | |||
5 PINS | 5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 224.9 | 220.4 | °C/W |
RθJCtop | Junction-to-case (top) thermal resistance | 95.2 | 89.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 51.4 | 46.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 6.6 | 5.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 50.3 | 46.2 | °C/W |
RθJCbot | Junction-to-case (bottom) thermal resistance | — | — | °C/W |
RθJACustom | See Power DIssipation and Junction Temperature | 139.3 | 134.9 | °C/W |
THERMAL METRIC(1) | TPS20xxC, TPS20xxC-2 | UNIT | |||
---|---|---|---|---|---|
DGN (MSOP-PowerPAD)(2) |
DGN (MSOP-PowerPAD)(3) |
DGK (VSSOP)(4) |
|||
8 PINS | 8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 72.1 | 67.1 | 205.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 87.3 | 80.8 | 94.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 42.2 | 37.2 | 126.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 7.3 | 5.6 | 24.7 | °C/W |
ψJB | Junction-to-board characterization parameter | 42 | 36.9 | 125.2 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 39.2 | 32.1 | — | °C/W |
RθJACustom | See Power DIssipation and Junction Temperature | 66.5 | 61.3 | 110.3 | °C/W |
PARAMETER | TEST CONDITIONS(1) | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
POWER SWITCH | |||||||
RDS(on) | Input – output resistance | 0.5-A rated output, 25°C | DBV | 97 | 110 | mΩ | |
0.5-A rated output, –40°C ≤ (TJ , TA) ≤ 85°C |
DBV | 96 | 130 | mΩ | |||
1-A rated output, 25°C | DBV | 96 | 110 | mΩ | |||
DGN | 86 | 100 | |||||
1-A rated output, –40°C ≤ (TJ , TA) ≤ 85°C |
DBV | 96 | 130 | mΩ | |||
DGN | 86 | 120 | |||||
1.5-A rated output, 25°C | DBV | 76 | 91 | mΩ | |||
DGN | 69 | 84 | mΩ | ||||
1.5-A rated output, –40°C ≤ (TJ , TA) ≤ 85°C |
DBV | 76 | 106 | mΩ | |||
DGN | 69 | 98 | mΩ | ||||
2-A rated output, 25°C | DGN, DGK | 72 | 84 | mΩ | |||
2-A rated output, –40°C ≤ (TJ , TA) ≤ 85°C | DGN, DGK | 72 | 98 | mΩ | |||
CURRENT LIMIT | |||||||
IOS(3) | Current limit, See Figure 6 |
0.5-A rated output | TPS20xxC | 0.67 | 0.85 | 1.01 | A |
1-A rated output | TPS20xxC | 1.3 | 1.55 | 1.8 | |||
TPS20xxC-2 | 1.18 | 1.53 | 1.88 | ||||
1.5-A rated output | TPS20xxC | 1.7 | 2.15 | 2.5 | |||
TPS20xxC-2 | 1.71 | 2.23 | 2.75 | ||||
2-A rated output | TPS20xxC | 2.35 | 2.9 | 3.4 | |||
SUPPLY CURRENT | |||||||
ISD | Supply current, switch disabled | IOUT = 0 A | 0.01 | 1 | µA | ||
–40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A | 2 | ||||||
ISE | Supply current, switch enabled | IOUT = 0 A | 60 | 70 | µA | ||
–40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A | 85 | ||||||
Ilkg | Leakage current | VOUT = 0 V, VIN = 5 V, disabled, measure IVIN | TPS20xxC-2 | 0.05 | 1 | µA | |
–40°C ≤ (TJ , TA) ≤ 85°C, VOUT = 0 V, VIN = 5 V, disabled, measure IVIN |
2 | ||||||
IREV | Reverse leakage current | VOUT = 5 V, VIN = 0 V, measure IVOUT | 0.1 | 1 | µA | ||
–40°C ≤ (TJ , TA) ≤ 85°C, VOUT = 5 V, VIN = 0 V, measure IVOUT | 5 | ||||||
OUTPUT DISCHARGE | |||||||
RPD | Output pulldown resistance(2) | VIN = VOUT = 5 V, disabled | TPS20xxC | 400 | 470 | 600 | Ω |
PARAMETER | TEST CONDITIONS(1) | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
POWER SWITCH | |||||||
RDS(ON) | Input – output resistance | 0.5-A rated output | DBV | 97 | 154 | mΩ | |
1-A rated output | DBV | 96 | 154 | mΩ | |||
DGN | 86 | 140 | |||||
1.5-A rated output | DBV | 76 | 121 | mΩ | |||
DGN | 69 | 112 | mΩ | ||||
2-A rated output | DGN, DGK | 72 | 112 | mΩ | |||
ENABLE INPUT (EN or EN) | |||||||
Threshold | Input rising | 1 | 1.45 | 2 | V | ||
Hysteresis | 0.07 | 0.13 | 0.2 | V | |||
Leakage current | (VEN or VEN) = 0 V or 5.5 V | –1 | 0 | 1 | µA | ||
CURRENT LIMIT | |||||||
IOS(3) | Current limit, See Figure 23 |
0.5-A rated output | TPS20xxC | 0.65 | 0.85 | 1.05 | A |
1-A rated output | TPS20xxC | 1.2 | 1.55 | 1.9 | |||
TPS20xxC-2 | 1.1 | 1.53 | 1.96 | ||||
1.5-A rated output | TPS20xxC | 1.6 | 2.15 | 2.7 | |||
TPS20xxC-2 | 1.6 | 2.23 | 2.86 | ||||
2-A rated output | TPS20xxC | 2.3 | 2.9 | 3.6 | |||
tIOS | Short-circuit response time(2) | VIN = 5 V (see Figure 6), One-half full load → RSHORT = 50 mΩ, Measure from application to when current falls below 120% of final value |
2 | µs | |||
SUPPLY CURRENT | |||||||
ISD | Supply current, switch disabled | IOUT = 0 A | 0.01 | 10 | µA | ||
ISE | Supply current, switch enabled | IOUT = 0 A | 65 | 90 | µA | ||
Ilkg | Leakage current | VOUT = 0 V, VIN = 5 V, disabled, measure IVIN |
TPS20XXC-2 | 0.05 | µA | ||
IREV | Reverse leakage current | VOUT = 5.5 V, VIN = 0 V, measure IVOUT | 0.2 | 20 | µA | ||
UNDERVOLTAGE LOCKOUT | |||||||
VUVLO | Rising threshold | VIN↑ | 3.5 | 3.75 | 4 | V | |
Hysteresis(2) | VIN↓ | 0.14 | V | ||||
FLT | |||||||
Output low voltage, FLT | IFLT = 1 mA | 0.2 | V | ||||
OFF-state leakage | VFLT = 5.5 V | 1 | µA | ||||
tFLT | FLT deglitch | FLT assertion or deassertion deglitch | 6 | 9 | 12 | ms | |
OUTPUT DISCHARGE | |||||||
RPD | Output pulldown resistance | VIN = 4 V, VOUT = 5 V, disabled | TPS20XXC | 350 | 560 | 1200 | Ω |
VIN = 5 V, VOUT = 5 V, disabled | TPS20XXC | 300 | 470 | 800 | |||
THERMAL SHUTDOWN | |||||||
Rising threshold (TJ) | In current limit | 135 | °C | ||||
Not in current limit | 155 | ||||||
Hysteresis (2) | 20 |
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
ENABLE INPUT (EN or EN) | |||||||
tON | Turnon time | VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↑ or EN ↓. See Figure 1, Figure 3, and Figure 4 |
0.5-A and 1-A Rated | 1 | 1.4 | 1.8 | ms |
1.5-A and 2-A Rated | 1.2 | 1.7 | 2.2 | ||||
tOFF | Turnoff time | VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↓ or EN ↑. See Figure 1, Figure 3, and Figure 4 |
0.5-A and 1-A Rated | 1.3 | 1.65 | 2 | ms |
1.5-A and 2-A Rated | 1.7 | 2.1 | 2.5 | ||||
tR | Rise time, output | CL = 1 µF, RL = 100 Ω, VIN = 5 V. See Figure 2 | 0.5-A and 1-A Rated | 0.4 | 0.55 | 0.7 | ms |
1.5-A and 2-A Rated | 0.5 | 0.7 | 1 | ||||
tF | Fall time, output | CL = 1 µF, RL = 100 Ω, VIN = 5 V. See Figure 2 | 0.5-A and 1-A Rated | 0.25 | 0.35 | 0.45 | ms |
1.-5A and 2-A Rated | 0.3 | 0.43 | 0.55 |
The TPS20xxC and TPS20xxC-2 are current-limited, power-distribution switches providing a range from 0.5 A and 2 A of continuous load current in 5-V circuits. These parts use N-channel MOSFETs for low resistance, maintaining voltage regulation to the load. They are designed for applications where short circuits or heavy capacitive loads are encountered. Device features include enable, reverse blocking when disabled, output discharge pulldown, overcurrent protection, overtemperature protection, and deglitched fault reporting.
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turnon threshold. Built-in hysteresis prevents unwanted ON/OFF cycling due to input voltage drop from large current surges. FLT is high impedance when the TPS20xxC and TPS20xxC-2 are in UVLO.
The logic enable input (EN, or EN), controls the power switch, bias for the charge pump, driver, and other circuits. The supply current is reduced to less than 1 µA when the TPS20xxC and TPS20xxC-2 are disabled. Disabling the TPS20xxC and TPS20xxC-2 immediately clears an active FLT indication. The enable input is compatible with both TTL and CMOS logic levels.
The turnon and turnoff times (tON, tOFF) are composed of a delay and a rise or fall time (tR, tF). The delay times are internally controlled. The rise time is controlled by both the TPS20xxC and TPS20xxC-2 and the external loading (especially capacitance). TPS20xxC fall time is controlled by the loading (R and C), and the output discharge (RPD). TPS20xxC-2 does not have the output discharge (RPD), fall time is controlled by the loading (R and C). An output load consisting of only a resistor experiences a fall time set by the TPS20xxC and TPS20xxC-2. An output load with parallel R and C elements experiences a fall time determined by the (R × C) time constant if it is longer than the tF TPS20xxC and TPS20xxC-2.
The enable must not be left open, and may be tied to VIN or GND depending on the device.
The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump supplies power to the gate driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The driver incorporates circuitry that controls the rise and fall times of the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start functionality. The MOSFET power switch blocks current from OUT to IN when turned off by the UVLO or disabled.
The TPS20xxC and TPS20xxC-2 responds to overloads by limiting output current to the static IOS levels shown in Electrical Characteristics: TJ = TA = 25°C. When an overload condition is present, the device maintains a constant output current, with the output voltage determined by (IOS × RLOAD). Two possible overload conditions can occur. The first overload condition occurs when either:
The output voltage is held near zero potential with respect to ground and the TPS20xxC and TPS20xxC-2 ramps the output current to IOS. The TPS20xxC and TPS20xxC-2 limits the current to IOS until the overload condition is removed or the device begins to thermal cycle. This is demonstrated in Figure 26 where the device was enabled into a short, and subsequently cycles current OFF and ON as the thermal protection engages.
The second condition is when an overload occurs while the device is enabled and fully turned on. The device responds to the overload condition within tIOS (Figure 5 and Figure 6) when the specified overload (see Electrical Characteristics: –40°C ≤ TJ ≤ 125°C) is applied. The response speed and shape varies with the overload level, input circuit, and rate of application. The current limit response will vary between simply settling to IOS, or turnoff and controlled return to IOS. Similar to the previous case, the TPS20xxC and TPS20xxC-2 limits the current to IOS until the overload condition is removed or the device begins to thermal cycle. This is demonstrated by Figure 27, Figure 28, and Figure 29.
The TPS20xxC and TPS20xxC-2 thermal cycles if an overload condition is present long enough to activate thermal limiting in any of the above cases. This is due to the relatively large power dissipation [(VIN – VOUT) × IOS] driving the junction temperature up. The device turns off when the junction temperature exceeds 135°C (minimum) while in current limit. The device remains off until the junction temperature cools 20°C and then restarts.
There are two kinds of current limit profiles typically available in TI switch products that are similar to the TPS20xxC and TPS20xxC-2. Many older designs have an output I vs V characteristic similar to the plot labeled Current Limit with Peaking in Figure 22. This type of limiting can be characterized by two parameters, the current limit corner (IOC), and the short circuit current (IOS). IOC is often specified as a maximum value. The TPS20xxC and TPS20xxC-2 family of parts does not present noticeable peaking in the current limit, corresponding to the characteristic labeled Flat Current Limit in Figure 22. This is why the IOC parameter is not present in Electrical Characteristics: –40°C ≤ TJ ≤ 125°C.
The FLT open-drain output is asserted (active low) during an overload or overtemperature condition. A 9-ms deglitch on both the rising and falling edges avoids false reporting at start-up and during transients. A current limit condition shorter than the deglitch period clears the internal timer upon termination. The deglitch timer does not integrate multiple short overloads and declare a fault. This is also true for exiting from a faulted state. An input voltage with excessive ripple and large output capacitance may interfere with operation of FLT around IOS as the ripple drives the TPS20xxC and TPS20xxC-2 in and out of current limit.
If the TPS20xxC and TPS20xxC-2 are in current limit and the overtemperature circuit goes active, FLT goes true immediately (see Figure 27); however, the exiting this condition is deglitched (see Figure 29). FLT is tripped just as the knee of the constant-current limiting is entered. Disabling the TPS20xxC and TPS20xxC-2 clears an active FLT as soon as the switch turns off (see Figure 26). FLT is high impedance when the TPS20xxC and TPS20xxC-2 are disabled or in undervoltage lockout (UVLO).
A 470-Ω (typical) output discharge dissipates stored charge and leakage current on OUT when the TPS20xxC is in UVLO or disabled. The pulldown circuit loses bias gradually as VIN decreases, causing a rise in the discharge resistance as VIN falls towards 0 V. The TPS20xxC-2 does not have this function. The output is be controlled by an external loadings when the device is in ULVO or disabled.
There are no other functional modes.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS20xxC and TPS20xxC-2 current-limited power switch uses N-channel MOSFETs in applications requiring continuous load current. The device enters constant-current mode when the load exceeds the current limit threshold.
For this design example, use the following input parameters:
To begin the design process a few parameters must be decided upon. The designer must know the following:
Input and output capacitance improves the performance of the device; the actual capacitance must be optimized for the particular application. For all applications, TI recommends placing a 0.1-µF or greater ceramic bypass capacitor between IN and GND, as close to the device as possible for local noise decoupling.
All protection circuits such as the TPS20xxC and TPS20xxC-2 has the potential for input voltage overshoots and output voltage undershoots.
Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high impedance (before turnon). Theoretically, the peak voltage is 2× the applied. The second cause is due to the abrupt reduction of output short-circuit current when the TPS20xxC and TPS20xxC-2 turns off and energy stored in the input inductance drives the input voltage high. Input voltage droops may also occur with large load steps and as the TPS20xxC and TPS20xxC-2 output is shorted. Applications with large input inductance (for example, connecting the evaluation board to the bench power-supply through long cables) may require large input capacitance reduce the voltage overshoot from exceeding the absolute maximum voltage of the device. The fast current limit speed of the TPS20xxC and TPS20xxC-2 to hard output short circuits isolates the input bus from faults. However, ceramic input capacitance in the range of 1 µF to 22 µF adjacent to the TPS20xxC and TPS20xxC-2 input aids in both speeding the response time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V are permitted.
Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred and the TPS20xxC and TPS20xxC-2 has abruptly reduced OUT current. Energy stored in the inductance drives the OUT voltage down and potentially negative as it discharges. Applications with large output inductance (such as from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. When implementing USB standard applications, a 120-µF minimum output capacitance is required. Typically a 150-µF electrolytic capacitor is used, which is sufficient to control voltage undershoots. However, if the application does not require 120 µF of capacitance, and there is potential to drive the output negative, then TI recommends a minimum of 10-µF ceramic capacitance on the output. The voltage undershoot must be controlled to less than 1.5 V for 10 µs.
Design of the devices is for operation from an input voltage supply range of 4.5 V to 5.5 V. The current capability of the power supply should exceed the maximum current limit of the power switch.
It is good design practice to estimate power dissipation and maximum expected junction temperature of the TPS20xxC and TPS20xxC-2. The system designer can control choices of package, proximity to other power dissipating devices, and printed-circuit board (PCB) design based on these calculations. These have a direct influence on maximum junction temperature. Other factors, such as airflow and maximum ambient temperature, are often determined by system considerations. It is important to remember that these calculations do not include the effects of adjacent heat sources, and enhanced or restricted air flow.
Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low as practical. The lower junction temperatures achieved by soldering the pad improve the efficiency and reliability of both TPS20xxC and TPS20xxC-2 parts and the system. The following examples were used to determine the θJACustom thermal impedances noted in Thermal Information: SOT-23 and Thermal Information: MSOP-PowerPAD. They were based on use of the JEDEC high-k circuit board construction (2 signal and 2 plane) with 4, 1-oz. copper weight, layers.
While TI recommends that the DGN package PAD be soldered to circuit board copper fill and vias for low thermal impedance, there may be cases where this is not desired. For example, use of routing area under the IC. Some devices are available in packages without the PowerPad (DGK) specifically for this purpose. The θJA for the DGN package with the pad not soldered and no extra copper, is approximately 141°C/W for 0.5-A and 1-A rated parts, and 139°C/W for the 1.5-A and 2-A rated parts. The θJA for the DGK mounted per Figure 45 is 110.3°C/W. These values may be used in Equation 1 to determine the maximum junction temperature.
As shown in Equation 1, the following procedure requires iteration because power loss is due to the internal MOSFET I2 × RDS(ON), and RDS(ON) is a function of the junction temperature. As an initial estimate, use the RDS(ON) at 125°C from the Typical Characteristics, and the preferred package thermal resistance for the preferred board construction from the Thermal Information: SOT-23 table.
where
If the calculated TJ is substantially different from the original assumption, estimate a new value of RDS(ON) using the typical characteristic plot and recalculate.
If the resulting TJ is not less than 125°C, try a PCB construction or a package with lower θJA.
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
PARTS | PRODUCT FOLDER | SAMPLE & BUY | TECHNICAL DOCUMENTS | TOOLS & SOFTWARE | SUPPORT & COMMUNITY |
---|---|---|---|---|---|
TPS2000C | Click here | Click here | Click here | Click here | Click here |
TPS2001C | Click here | Click here | Click here | Click here | Click here |
TPS2041C | Click here | Click here | Click here | Click here | Click here |
TPS2051C | Click here | Click here | Click here | Click here | Click here |
TPS2061C | Click here | Click here | Click here | Click here | Click here |
TPS2065C | Click here | Click here | Click here | Click here | Click here |
TPS2065C-2 | Click here | Click here | Click here | Click here | Click here |
TPS2068C | Click here | Click here | Click here | Click here | Click here |
TPS2069C | Click here | Click here | Click here | Click here | Click here |
TPS2069C-2 | Click here | Click here | Click here | Click here | Click here |
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.