SLVSGU5A April   2022  – July 2022 TPS22811

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
      1.      14
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO and UVP)
      2. 7.3.2 Overvoltage Lockout (OVLO)
      3. 7.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 7.3.3.1 Slew Rate (dVdt) and Inrush Current Control
        2. 7.3.3.2 Short-Circuit Protection
        3. 7.3.3.3 Active Current Limiting During Start-Up
      4. 7.3.4 Analog Load Current Monitor
      5. 7.3.5 Overtemperature Protection (OTP)
      6. 7.3.6 Fault Response
      7. 7.3.7 Power-Good Indication (PG)
      8. 7.3.8 Quick Output Discharge (QOD)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Single Device, Self-Controlled
      2. 8.1.2 Parallel Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting Undervoltage and Overvoltage Thresholds
        2. 8.2.2.2 Setting Output Voltage Rise Time (tR)
        3. 8.2.2.3 Setting Power-Good Assertion Threshold
        4. 8.2.2.4 Setting Analog Current Monitor Voltage (IMON) Range
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Transient Protection
    2. 9.2 Output Short-Circuit Measurements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6 Fault Response

The following table summarizes the device response to various fault conditions.

Table 7-2 Fault Summary

Event

Protection Response

Fault Latched Internally

Overtemperature

Shutdown

Y

Undervoltage (UVP or UVLO)

Shutdown

N

Input overvoltage

 Shutdown

N

Output short circuit to GND

Fast-trip

Y

Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V) or by pulling the EN/UVLO pin voltage below VSD.

During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device.