9.3.1 On and Off Control (EN pin)

The EN pin controls the state of the switch. When the voltage on EN has exceeded V_IH,EN the switch is enabled. When EN goes below V_IL,EN the switch is disabled.

The EN pin has a blanking time of t_BLANK on the rising edge once the V_IH,EN threshold has been exceeded. It also has a de-glitch time of t_DEGLITCH when the voltage has gone below V_IL,EN.

The EN pin can also be configured via an external resistor divider to monitor a voltage signal for input UVLO. See Equation 1 and Figure 53 on how to configure the EN pin for input UVLO.

Equation 1.

where

• V_IH,EN is the rising threshold of the EN pin (see the Electrical Characteristics table)
• V_IN is the input voltage being monitored (this could be V_IN, V_BIAS, or an external power supply)
• R_EN1, R_EN2 is the resistor divider values

Figure 53. Resistor Divider (EN Pin)

9.3.2 Voltage Monitoring (SNS Pin)

The SNS pin of the device can be used to monitor the output voltage of the device or another voltage rail. The pin can be configured with an external resistor divider to set the desired trip point for the voltage being monitored or be tied to OUT directly. If the voltage on the SNS pin exceeds V_IH,SNS, the voltage being monitored on the SNS pin is considered to be valid high. The voltage on the SNS pin must be greater than V_IH,SNS for at least t_BLANK before PG is asserted high. If the voltage on the SNS pin goes below V_IL,SNS, then the switch powers cycle (i.e., the switch is disabled and re-enabled). For proper functionality of the device, this pin must not be left floating. If a resistor divider is not being used for voltage sensing, this pin can be tied directly to V_OUT.

The SNS pin has a blanking time of t_BLANK on the rising edge once the V_IH,SNS threshold has been exceeded. It has a de-glitch time of t_DEGLITCH when the voltage has gone below V_IL,SNS.

See Equation 2 and Figure 54 on how to configure the SNS pin for voltage monitoring.

Equation 2.

where

• V_IH,SNS is the the rising threshold of the SNS pin (see Electrical Characteristics table)
• V_OUT is the voltage on the OUTpin
• R_SNS1, R_SNS2 is the resistor divider values

Figure 54. Voltage Divdier (SNS Pin)

9.3.3 Power Good (PG Pin)

The PG pin is only asserted high when the voltage on EN has exceeded V_IH,EN and the voltage on SNS has exceeded V_IH,SNS. There is a t_BLANK time, typically 100 µs, between the SNS voltage exceeding V_IH,SNS and PG being asserted high. If the voltage on EN goes below V_IL,EN or the voltage on SNS goes below V_IL,SNS, PG is de-asserted. There is a t_DEGLITCH time, typically 5µs, between the EN voltage or SNS voltage going below their respective V_IL levels and PG being pulled low.

PG is an open drain pin and must be pulled up with a pull-up resistor. Be sure to never exceed the maximum operating voltage on this pin. If PG is not being used in the application, tie it to GND for proper device functionality.

For proper PG operation, the BIAS voltage must be within the recommended operating range. In systems that are very sensitive to noise or have long PG traces, it is recommended to add a small capacitance from PG to GND for decoupling.

9.3.4 Supervisor Fault Detection and Automatic Restart

The falling edge of the SNS pin below V_IL,SNS is considered a fault case and causes the load switch to be disabled for t_RESTART (typically 2 ms). After the t_RESTART time, the switch is automatically re-enabled as long as EN is still above V_IH,EN . In the case the SNS pin is being used to monitor V_OUT or a downstream voltage, the restart helps to protect against excessive over-current if there is a quick short to GND. See Figure 55.

Figure 55. Automatic Restart after Quick Short to GND

9.3.5 Manual Restart

The falling edge of the SNS pin below V_IL,SNS is considered a fault case and causes the load switch to be disabled for t_RESTART (typically 2 ms). The SNS pin can be driven by an MCU to manually reset the load switch. After the t_RESTART time, the switch is automatically re-enabled as long as EN is still above V_IH,EN , even is SNS is held low. The PG pin stays low until the switch is re-enabled and the SNS pin rises above V_IH,SNS. See Figure 56.

Figure 56. Manual Restart (SNS Held Low)

If the SNS pin is brought above V_IH,SNS within the t_RESTART time, the switch still waits to re-enable. The PG pin also stays low until t_BLANK after switch is re-enabled. In this case, PG indicates when the switch is enabled and capable of being reset again. See Figure 57.

Figure 57. Manual Restart (SNS Toggled Low to High)

9.3.6 Thermal Shutdown

If the junction temperature of the device exceeds T_SD, the switch is disabled. The device is enabled once the junction temperature drops by TSD_HYS as long as EN is still greater than V_IH,EN.

9.3.7 Reverse Current Blocking (TPS22953 Only)

When the switch is disabled (either by de-asserting EN or SNS, triggering thermal shutdown, or losing power), the reverse current blocking (RCB) feature of the device is engaged within t_RCB, typically 10 μs. Once the RCB is engaged, the reverse current from the OUT pin to the IN pin is limited to I_RCB,IN, typically 0.01 μA.

9.3.8 Quick Output Discharge (QOD) (TPS22954 Only)

The quick output discharge (QOD) transistor is engaged indefinitely whenever the switch is disabled and the recommended V_BIAS voltage is met. During this state, the QOD resistance (R_PD) discharges V_OUT to GND. It is not recommended to apply a continuous DC voltage to OUT when the device is disabled.

The QOD transistor can remain active for a short period of time even after V_BIAS loses power. This brief period of time is defined as t_DIS. For best results, it is recommended the device get disabled before V_BIAS goes below the minimum recommended voltage. The waveform in Figure 58 shows the behaviour when power is applied and then removed in a typical application.

Figure 58. Power Applied and then Removed in a Typical Application

At the end of the t_DIS time, it is not guaranteed that V_OUT will be 0 V since the final voltage is dependent upon the initial voltage and the C_L capacitor. The final V_OUT can be calculated with Equation 3 for a given initial voltage and C_L capacitor.

Equation 3.

where

• V_f is the final V_OUT voltage
• V_o is the initial V_OUT voltage
• R is the the value of the output discharge resistor, R_PD (see the Electrical Characteristics table)
• C is the output bulk capacitance on OUT

9.3.9 V_IN and V_BIAS Voltage Range

For optimal R_ON performance, make sure V_IN ≤ V_BIAS. The device is still functional if V_IN > V_BIAS but it exhibits R_ON greater than what is listed in the Electrical Characteristics table. See Figure 59 for an example of a typical device. Notice the increasing R_ON as V_IN increases. Be sure to never exceed the maximum voltage rating for V_IN and V_BIAS.

Figure 59. R_ON When V_IN > V_BIAS

9.3.10 Adjustable Rise Time (CT pin)

A capacitor to GND on the CT pin sets the slew rate for V_OUT. An appropriate capacitance value must be placed on CT such that the I_MAX and I_PLS specifications of the device are not violated. The capacitor to GND on the CT pin must be rated for 25 V or higher. An approximate formula for the relationship between CT (except for CT = open) and the slew rate for any V_BIAS is shown in Equation 4.

Rise time can be calculated by multiplying the input voltage (typically 10% to 90%) by the slew rate. Table 1 contains rise time values measured on a typical device.

9.3.11 Power Sequencing

The TPS2295x operates regardless of power-on and power-off sequencing order. The order in which voltages are applied to IN, BIAS, and EN will not damage the device as long as the voltages do not exceed the absolute maximum operating conditions. If voltage is applied to EN before IN and BIAS, the slew rate of VOUT will not be controlled. Also, turning off IN and/or BIAS while EN is high will not damage the device.

Table 2. Function Table