SLVSCP7B November 2014 – March 2016 TPS22968-Q1
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
This section highlights some of the design considerations for implementing this device in various applications. A PSPICE model for this device is also available on the product page on www.ti.com for further aid. (See the Device Support section for more information)
To limit the voltage drop on the input supply caused by transient inrush currents when the switch turns on into a discharged load capacitor, a capacitor must be placed between VIN and GND. A 1-µF ceramic capacitor, CIN, placed close to the pins, is usually sufficient. Higher values of CIN can be used to further reduce the voltage drop during high-current applications. When switching heavy loads, TI recommends to have an input capacitor about 10× higher than the output capacitor to avoid excessive voltage drop.
Due to the integrated body diode in the NMOS switch, TI highly recommends a CIN greater than CL. A CL greater than CIN can cause the voltage on VOUT to exceed VIN when the system supply is removed. This could result in current flow through the body diode from VOUT to VIN. TI recommends a CIN to CL ratio of 10 to 1 for minimizing VIN dip caused by inrush currents during startup.
For optimal RON performance, make sure VIN ≤ VBIAS. The device is still functional if VIN > VBIAS, but it will exhibit RON greater than what is listed in the Electrical Characteristics (VBIAS = 5 V) and Electrical Characteristics (VBIAS = 2.5 V) . See Figure 35 for an example of a typical device. Notice the increasing RON as VIN exceeds VBIAS voltage. Be sure to never exceed the maximum voltage rating for VIN and VBIAS.
TA = 25°C | IOUT = –200 mA |
To increase the current capabilities and lower the RON by approximately 50%, both channels can be placed in parallel as shown in Figure 36 (parallel configuration). With this configuration, the CT1 and CT2 pins can be tied together to use one capacitor, CT, as shown in Figure 36. With a single CT capacitor, the rise time will be half of the typical rise-time value. Refer to the Table 1 for typical timing values.
TPS22968x-Q1 can help to reduce the standby power consumption of a module. Some loads will consume a non-trivial amount of power when turned off. If the power to the load is removed by the load switch, the standby power consumption can be significantly reduced. Figure 37 below shows the Standby Power Reduction Schematic.
In many end equipments, there is a need to power up various modules in a predetermined manner. TPS22968x-Q1 can solve the problem of power sequencing without adding any complexity to the overall system. See Figure 38.
In certain applications, it may be desirable to have reverse current blocking. Reverse current blocking prevents current from flowing from the output to the input of the load switch when the device is disabled. With the following configuration, the TPS22968x-Q1 can be converted into a single-channel switch with reverse current blocking. In this configuration, VIN1 or VIN2 can be used as the input and VIN2 or VIN1 is the output. See Figure 39.
This application demonstrates how the TPS22968x-Q1 can be used to power a downstream load with a large capacitance. The example in Figure 40 is powering a 22-µF capacitive output load.
For this design example, use the values listed in Table 3 as the input parameters.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
VIN | 3.3 V |
VBIAS | 5 V |
Output capacitance (CL) | 22 µF |
Allowable inrush current on VOUT | 0.4 A |
To begin the design process, the designer must know the following:
To determine how much inrush current will be caused by the CL capacitor, use Equation 2.
where
Inrush current is proportional to rise time. The rise time is adjustable by use of the CT capacitor. The appropriate rise time can be calculated using the design requirements and the inrush current equation ( Equation 2).
To ensure an inrush current of less than 400 mA, choose a CT capacitor value that will yield a rise time of more than 182 µs. See the oscilloscope captures in the Application Curves for an example of how the CT capacitor can be used to reduce inrush current. See Table 1 for correlation between rise times and CT values.
An appropriate CL value should be placed on VOUT such that the IMAX and IPLS specifications of the device are not violated.
The two scope captures in Figure 41 and Figure 42 show how the CT capacitor can be used to reduce inrush current.
VBIAS = 5 V | VIN = 3.3 V | TA = 25°C |
CT = Open | CL = 22 µF |
VBIAS = 5 V | VIN = 3.3 V | TA = 25°C |
CT = 220 pF | CL = 22 µF |