SLVSDX2A September   2017  – December 2017 TPS23521

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Relationship between Sense Voltage, Gate Current, and Timer
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Current Limit
        1. 8.3.1.1 Programming the CL Switch-Over Threshold
        2. 8.3.1.2 Setting Up the PROG Pin
        3. 8.3.1.3 Programming CL1
        4. 8.3.1.4 Programming CL2
      2. 8.3.2 Soft Start Disconnect
      3. 8.3.3 Timer
      4. 8.3.4 Gate 2
    4. 8.4 Device Functional Modes
      1. 8.4.1 OFF State
      2. 8.4.2 Insertion Delay State
      3. 8.4.3 Start-up State
      4. 8.4.4 Normal Operation State
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting RSNS
        2. 9.2.2.2 Selecting Soft Start Setting: CSS and CSS,VEE
        3. 9.2.2.3 Selecting VDS Switch Over Threshold
        4. 9.2.2.4 Timer Selection
        5. 9.2.2.5 MOSFET Selection and SOA Checks
        6. 9.2.2.6 EMI Filter Consideration
        7. 9.2.2.7 Under Voltage and Over Voltage Settings
        8. 9.2.2.8 Choosing RVCC and CVCC
        9. 9.2.2.9 Power Good Interface to Downstream DC/DC
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.4 Timer Selection

The timer determines how long the hot swap can be in current limit before timing out and can be programmed using CTMR. In general a longer time out (TTO) improves ability to ride through voltage steps, brown outs, and other transients. However, a larger setting can also expose the MOSFET to more stress, because it takes longer for the FET to shut down during fault conditions. If there are no specific voltage step or transient requirements, 2 ms is a good starting point. Use the equation below to compute the target CTMR. Choose the next available capacitor value of 15 nF, which results in a 2.25 ms time out.

Equation 16. TPS23521 tps23521_equation6.gif