7.4.8 Advanced Startup and Converter Operation

The internal PoE UVLO (Undervoltage Lock Out) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the downstream converter circuits from loading the PoE input during detection and classification. The converter circuits will discharge C_BULK while the PD is unpowered. Thus V_(VDD-RTN) will be a small voltage just after full voltage is applied to the PD, as seen in Figure 24. The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When V_VDD rises above the UVLO turn-on threshold (V_{UVLO_R}, approximately 38 V) with RTN high, the TPS2373-3 and TPS2373-4 enables the hotswap MOSFET with inrush current limit (~200 mA for TPS2373-3 and ~335 mA for TPS2373-4) as seen in Figure 26. The PG pin is in low state while C_BULK charges and V_RTN falls from V_VDD to nearly V_VSS. VC_OUT output is also turned off during that time, providing no low supply voltage to the PWM controller,to avoid additional loading between V_VDD and V_RTN that could prevent successful PD and subsequent converter start up. Once the inrush current falls about 10% below the inrush current limit, the PD current limit switches to the operational level (approximately 1.85 A for TPS2373-3 and approximately 2.2 A for TPS2373-4).

Additionally, as seen in Figure 26 once the inrush period duration has also exceeded ~81.5 ms, PG output becomes high impedance and the PWM controller startup source is turned on charging C_{VC_OUT}, the VC_OUT capacitor, and allowing the downstream converter circuitry to start. As seen in Figure 27, the converter soft-start introduces a slight additional delay before the start of switching. Note that the startup source current capability is such that it can fully maintain V_{VC_OUT} during the converter soft-start without requiring any significant C_{VC_OUT} capacitance. Once V_{VC_IN} has risen above V_{VCIN_ON} (~8.5 V), meaning that the DC-DC converter has ramped up its output voltage, VC_IN pin is internally connected to VC_OUT pin. The startup current source is then turned off ~24 ms (t_TPLHBT) later, completing the startup. TPH, TPL and BT outputs are enabled within t_TPLHBT following V_{VC_IN} rising above V_{VCIN_ON}. If there is a fault condition preventing V_{VC_IN} from rising during converter startup (for example a short-circuit at the output of the downstream converter), a t_{STUP_OUT} (~50 ms) timeout period is applied at the end of which the startup source is turned off and the VC switch is turned on, until V_{VC_OUT} falls below V_{VCO_UV} to initiate a new startup cycle.

The falling VC_OUT UVLO threshold (V_{VCO_UV}) needs to be below the minimum falling UVLO threshold of the PWM controller, to ensure that every time the TPS2373 initiates a new startup cycle, the PWM controller has already reached a reset state and will initiate a new soft-start sequence. V_{VCO_UV} is selectable between nominally 6.9 V and 3.9 V, via the UVLO_SEL input, to accommodate various PWM controllers.

Figure 26. Power Up and Start

Figure 27. Power Up and Start

If V_VDD-V_VSS drops below the lower PoE UVLO (V_{UVLO_F}, ~32 V), the hotswap switch is turned off, but the PG output remains high impedance allowing the converter to continue operating until V_{VC_OUT} falls below the PWM controller's UVLO threshold. See VC Input and Output, CVCIN and CVCOUT for general guidance on how to handle PoE shutdown conditions.