SLVSB97E July   2012  – January 2018 TPS23751 , TPS23752

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1. 3.1 Typical Application Circuit
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings: Surge
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electric Characteristics - Controller Section
    7. 6.7 Electrical Characteristics - Sleep Mode (TPS23752 Only)
    8. 6.8 Electrical Characteristics - PoE Interface Section
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Pin Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 PoE Overview
        1. 7.4.1.1 Threshold Voltages
        2. 7.4.1.2 PoE Startup Sequence
        3. 7.4.1.3 Detection
        4. 7.4.1.4 Hardware Classification
        5. 7.4.1.5 Inrush and Startup
        6. 7.4.1.6 Maintain Power Signature
        7. 7.4.1.7 Startup and Converter Operation
        8. 7.4.1.8 PD Hotswap Operation
      2. 7.4.2 Sleep Mode Operation (TPS23752 only)
        1. 7.4.2.1  Converter Controller Features
        2. 7.4.2.2  PWM and VFO Operation; CTL, SRT, and SRD Pin Relationships to Output Load Current
        3. 7.4.2.3  Bootstrap Topology
        4. 7.4.2.4  Current Slope Compensation and Current Limit
        5. 7.4.2.5  RT
        6. 7.4.2.6  T2P, Startup and Power Management
        7. 7.4.2.7  Thermal Shutdown
        8. 7.4.2.8  Adapter ORing
        9. 7.4.2.9  Using DEN to Disable PoE
        10. 7.4.2.10 ORing Challenges
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistor, RCLS
        6. 8.2.2.6  APD Pin Divider Network, RAPD1, RAPD2
        7. 8.2.2.7  Setting the PWM-VFO Threshold using the SRT pin
        8. 8.2.2.8  Setting Frequency (RT)
        9. 8.2.2.9  Current Slope Compensation
        10. 8.2.2.10 Voltage Feed-Forward Compensation
        11. 8.2.2.11 Estimating Bias Supply Requirements and Cvc
        12. 8.2.2.12 Switching Transformer Considerations and RVC
        13. 8.2.2.13 T2P Pin Interface
        14. 8.2.2.14 Softstart
        15. 8.2.2.15 Special Switching MOSFET Considerations
        16. 8.2.2.16 ESD
        17. 8.2.2.17 Thermal Considerations and OTSD
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electric Characteristics - Controller Section

Unless otherwise noted, 40 V ≤ VDD ≤ 57 V; VCTL = VMODE = VSLPb = VB; VSRT = 0.5 V; VAPD = VCS = VARTN = VRTN; CLS, GATE, LED, SRD, T2P open; RWAKE = 392 kΩ; RDEN = 24.9 kΩ; RT = 34 kΩ; CVB = CVC = 0.1 µF;
–40 ≤ TJ ≤ 125°C. Typical values are at 25°C. All voltages referred to VSS.
VC = 12 V, VDEN = VVSS, VARTN = VRTN = VSS
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VC (GATE DRIVE SUPPLY)
Output voltage; TPS23752 only VVDD = 48 V, Sleep mode 12 12.8 13.8 V
IVC_ST Startup source current VVDD = 48 V, VC = 0 V 1.1 1.5 2.1 mA
VVDD = 10.9 V, VC = 8.6 V 0.9 1.3 1.8
IVC_OP Operating current VVC = 12 V, VCTL = VB 0.9 1.8 3.0 mA
tST Bootstrap start up time, CVC = 22 µF VVDD = 48 V, measure time from VVC (0) → VCUV 103 155 203 ms
VCUV UVLO threshold VVC rising until VSRD ↓ 8.6 8.9 9.2 V
VCUVH Hysteresis 3 3.2 3.4 V
VB (BIAS SUPPLY)
Output voltage 7.5 V ≤ VVC ≤ 18 V, 0 ≤ IVB ≤ 5 mA 4.75 5.00 5.25 V
APD (AUXILIARY POWER DETECT)
VAPDEN APD threshold voltage VAPD ↑, measure with respect to ARTN 1.43 1.50 1.57 V
VAPDH Hysteresis 0.28 0.30 0.32 V
Leakage current VAPD = 18 V 10 µA
RT (OSCILLATOR)
FSW Switching frequency in PWM mode RT = 34.0 kΩ. Measure at GATE 226 251 276 kHz
FVFO Switching frequency in VFO mode VCTL = 1.75 V, RT = 34.0 kΩ. Measure at GATE 105 135 165 kHz
DMAX Maximum duty cycle VCTL = VB, Measure at GATE 75% 80% 85%
CTL (CONTROL – PWM INPUT)
VCTL_VFO VCTL at PWM/VFO transition point VSRT = 0.5 V VCTL ↓ until VSRD↑ 1.90 2.00 2.10 V
Hysteresis (1) 35 mV
VSRT = 1.0 V VCTL ↓ until VSRD↑ 2.15 2.25 2.35 V
Hysteresis (1) 40.50 mV
TSSD Internal soft start delay time VCTL = 3.5 V, measure from switching start to VCSMAX 1.87 3.01 5.09 ms
Input resistance 70 105 145 kΩ
VZF Zero frequency threshold (ZF) VCTL ↓ until GATE stops switching 1.40 1.50 1.60 V
VZDC Zero duty cycle (ZDC) threshold (VFO disabled) VSRT = VARTN, VCTL ↓ until GATE stops switching 1.55 1.75 1.95 V
Gain, VCS to VCTL(1) 5.0 V/V
CS (CURRENT SENSE)
VCSMAX Maximum threshold voltage VCS↑ until VGATE ↓ 0.22 0.25 0.28 V
VCS_VFO Peak VCS in VFO mode 1.60 V ≤ VCTL ≤ 1.90 V, VSRT = 0.5 V, VCS ↑ until VGATE↓ 40 50 60 mV
1.85 V ≤ VCTL ≤ 2.15 V, VSRT = 1.0 V, VCS↑ until VGATE ↓ 85 100 115 mV
VPK Internal slope compensation voltage, see Figure 1 D = DMAX 32 40 50 mV
ICS_RAMP Ramp component of ICS D = DMAX 12 16 25 µA
ICSDC DC component of ICS 1 2 3 µA
DSLOPE_ST Slope compensation ramp start relative to switching period. Refer to Figure 1 30% 34% 39%
t1 Turn off delay VCS = 0.3 V, measure tprf50–50, see Figure 2 50 90 ns
tBLNK Blanking period 100 150 200 ns
Off state pulldown resistance 290 500 Ω
GATE (GATE DRIVER)
Peak source current GATE high, pulsed measurement 0.35 0.60 1.00 A
Peak sink current GATE low, pulsed measurement 0.70 1.00 1.40 A
Rise time (1) tprr10–90, CGATE = 1 nF; see Figure 3 40 ns
Fall time (1) tpff90–10, CGATE = 1 nF; see Figure 3 27 ns
Pull-up resistance 20 Ω
Pull-down resistance 10 Ω
SRD (SYNCHRONOUS RECTIFIER DISABLE)
Output low voltage ISRD = 2 mA sinking 0.25 0.45 V
Leakage current VCTL = 1.75 V, VSRD = 18 V 10 µA
SRT (SYNCHRONOUS RECTIFIER THRESHOLD)
Leakage current 0 V ≤ VSRT ≤ 5 V 1 µA
THERMAL SHUTDOWN
Shutdown TJ rising 135 145 155 °C
Hysteresis(1) 20 °C
(1) Parameters provided for reference only, and do not constitute part of TI published specifications for purposes of TI product warranty.