7.3.1 Pin Description

The following descriptions refer to the functional block diagrams.

APD: (Auxiliary Power Detect): The APD pin is used in applications that may draw power either from the Ethernet cable or from an auxiliary power source. A voltage of more than about 1.5 V on the APD pin relative to RTN turns off the internal pass MOSFET, disables the CLS output, and enables the T2P output. A resistor divider (R_APD1 – R_APD2 in Figure 31) provides system-level ESD protection for the APD pin, discharges leakage from the blocking diode (D_A in Figure 31), and provides input voltage supervision to ensure that switch-over to the auxiliary voltage source does not occur at excessively low voltages. If not used, connect APD to ARTN. When the TPS23752 operates in Sleep Mode, holding APD higher than its rising threshold, V_APDEN, disables the maintain power signature (MPS).

ARTN: The ARTN pin is the local ground return for the DC-DC controller. Connections to the ARTN pin should return to a local ground plane beneath the DC-DC converter primary circuitry. For most applications, this ground plane should also connect to RTN.

CLS: An external resistor (R_CLS in Figure 31) connected between the CLS pin and V_SS provides a classification signature to the PSE. The controller places a voltage of approximately 2.5 V across the external resistor whenever the voltage differential between V_DD and V_SS lies between about 10.9 V and 22 V. The current drawn by this resistor, combined with the internal current drain of the controller and any leakage through the internal pass MOSFET, creates the classification current. Table 1 lists the external resistor values required for each of the PD power ranges defined by IEEE802.3at. The maximum average power drawn by the PD, including all losses within the DC-DC converter as well as power supplied to the downstream load, should not exceed the maximum power indicated in Table 1. Holding APD high disables the classification signature.

High-power PSEs may perform two classification cycles if Class 4 is presented on the first cycle.

CS (Current Sense): The CS pin serves as the current sense input for the DC-DC controller. The CS pin senses the voltage at the high side of the current sense resistor (R_CS in Figure 31). This voltage drives the current limit comparator and the PWM comparator (see Block Diagram of DC-DC controller). A leading-edge blanking circuit prevents MOSFET turn-on transients from falsely triggering either of these comparators. During the off time, and also during the blanking time that immediately follows, the CS pin is pulled to ARTN through an internal pulldown resistor.

The current limit comparator terminates the on-time portion of the switching cycle as soon as V_CS exceeds approximately 250 mV and the leading edge blanking interval has expired. If the converter is not in current limit, then either the PWM comparator or the maximum duty cycle limiting circuit terminates the on time.

An internal slope compensation circuit generates a current that imposes a voltage ramp at the positive input of the PWM comparator to suppress sub-harmonic oscillations. This current flows out of the CS pin. If desired, the magnitude of the slope compensation can be increased by the addition of an external resistor in series with the CS pin. The beginning of the slope compensation ramp is delayed to provide a smoother transition from PWM to VFO mode, as shown in Figure 1. Slope compensation, including that generated by any external resistance, is disabled in VFO mode.

CTL (Control): The CTL pin receives the control voltage from the external error amplifier. Typically this error amplifier consists of a TL431 shunt regulator driving an optocoupler, but other configurations are possible. The voltage differential between CTL and ARTN regulates power flow through the DC-DC converter. The voltage V_{CTL_VFO} set by the SRT pin represents the boundary between PWM and VFO mode. In the PWM mode of operation, the CTL voltage determines the threshold at which the PWM comparator terminates the on-time interval. During VFO mode, the inductor peak current is fixed and the CTL voltage varies the switching frequency. During PWM mode the switching frequency is fixed and the CTL voltage varies the duty cycle.

DEN (Detection and Enable): The DEN pin implements two separate functions. A resistor (R_DEN in Figure 31) connected between V_DD and DEN generates a detection signature whenever the voltage differential between V_DD and V_SS lies between approximately 1.4 and 10.9 V. Beyond this range, the controller disconnects this resistor to save power. For applications that wish to comply with the requirements of IEEE802.3at, the external resistance should equal 24.9 kΩ.

If the resistance connected between V_DD and DEN is divided into two roughly equal portions, then the application circuit can disable the PD by grounding the tap point between the two resistances. This action simultaneously spoils the detection signature and thereby signals the PSE that the PD no longer requires power.

GATE: The gate drive pin drives the main switching MOSFET of the DC-DC converter. The internal gate driver circuitry draws power from V_C and returns it to ARTN. GATE is held low whenever the converter is disabled.

LED (TPS23752 only): The LED pin drives an external status LED. Connect the LED and its series current-limiting resistor from V_C to the LED pin. While in Sleep Mode, the controller pulls the LED pin to ARTN. The LED pin is also pulled low during normal operation after the soft start is complete whenever the MODE pin is low. The LED pin should draw as little current as possible to help minimize the power consumed by the PD in Sleep Mode. If a status LED is not required, leave this pin open.

MODE (TPS23752 only): The MODE pin in combination with the SLPb pin sets the type of MPS (DC or pulsed) during Sleep Mode. Holding this pin high when the SLPb pin transitions low causes the TPS23752 to generate a DC MPS by drawing a total of 10.6 mA (typical) from the Ethernet cable. Holding this pin low when the SLPb pin transitions low causes the TPS23752 to generate a pulsed MPS. Either MPS ensures that the PSE does not disconnect power from the PD while it is asleep. An MPS is not generated if the APD pin is held high (> 1.5 V). During normal operation, pulling MODE low causes the LED pin to pull low.

RT (Timing Resistor): A timing resistor (R_T in Figure 31) connected between this pin and ARTN sets the PWM switching frequency f_SW according to Figure 31.

Equation 1.

The switching frequency remains constant during PWM operation, but decreases as V_CTL falls below V_{CTL_VFO}. RT is a high impedance pin. Keep the connections short and isolate them from potential noise sources.

RTN: The RTN pin provides the negative power return path for the converter. Once V_DD exceeds the UVLO threshold (V_{UVLO_R}), the internal pass MOSFET pulls RTN to VSS. Inrush limiting prevents the RTN current from exceeding about 140 mA until the bulk capacitance (C_IN in Figure 31) is fully charged. Inrush ends and the converter begins operating when the RTN current drops below about 125 mA. The RTN current is subsequently limited to about 1 A. If RTN ever exceeds about 12 V, then the controller returns to inrush limiting.

RTN should be connected to ARTN for most applications.

SLPb: (TPS23752 only): The SLPb pin controls entry into Sleep Mode. A falling-edge transition applied to this pin during normal operation initiates Sleep Mode. This mode of operation disables converter switching, increases the current limit of the internal V_C regulator, and pulls the LED output low. Cycling V_DD or pulling the WAKE pin low terminates the Sleep Mode and restores normal operation.

SRD (Synchronous Rectifier Disable): This open-drain output pulls to ARTN whenever the DC-DC converter is enabled, inrush and soft start are complete, and the voltage at the CTL pin exceeds the threshold V_{CTL_VFO} set by the SRT pin. A low voltage on the SRD pin signals the synchronous rectifier to begin operation. If the CTL pin voltage drops below V_{CTL_VFO}, then the SRD output goes high impedance to disable the synchronous rectifier. This action ensures that the synchronous rectifier does not operate during VFO mode.

SRT (Synchronous Rectifier Threshold): The SRT pin sets the thresholds V_{CTL_VFO} and V_{CS_VFO}, at which the DC-DC converter switches between PWM and VFO. The application circuit normally uses a resistor divider (R_SRT1 – R_SRT2 in Figure 31) to generate a voltage of 0.5 to 1.5 V at the SRT pin. When the voltage on the CTL pin exceeds V_{CTL_VFO}, the converter operates in PWM mode and the SRD pin is pulled low to enable the synchronous rectifier. When the voltage on CTL falls below V_{CTL_VFO}, the converter operates in VFO and the SRD pin goes high impedance to disable the synchronous rectifier. Tying SRT to ARTN disables the VFO mode.

T2P (Type-2 PSE Indicator): The controller pulls this pin to ARTN whenever type-2 hardware classification has been observed; or the APD pin is pulled high, after the internal T2P delay is complete, and V_CTL ≤ 4 V. Once T2P is valid, V_CTL has no effect on the status of T2P. The T2P output will return to a high-impedance state if the part enters thermal shutdown, the pass MOSFET enters inrush limiting, or if a type-2 PSE was not detected and the voltage on APD drops below its threshold. The circuitry that watches for type-2 hardware classification latches its result when the V_(VDD-VSS) voltage differential rises above the upper classification threshold. This circuit resets when the V_(VDD-VSS) voltage differential drops below the mark threshold. The T2P pin can be left unconnected if it is not used.

V_B (Bias Voltage): The V_B pin is the output of an internal 5 V regulator fed from V_C. A ceramic bypass capacitor with a minimum capacitance of no less than 80 nF must connect from V_B to ARTN. V_B may be used to bias the feedback optocoupler. For the TPS23752, V_B may also bias pullups for SLPb and MODE.

V_C (Controller Voltage): The V_C pin connects to the auxiliary bias supply for the DC-DC controller. The MOSFET gate driver draws current directly from V_C. V_B is regulated down from V_C to provide power for the rest of the internal control circuitry. A startup current source from V_DD to V_C controlled by a comparator with hysteresis implements the converter bootstrap startup. V_C must receive power from an auxiliary source, such as an auxiliary winding on the flyback transformer, to sustain normal operation after startup. A low-ESR bypass capacitor, such as a ceramic capacitor, must connect from V_C to ARTN to supply the gate drive current required to drive the external switching MOSFET.

The TPS23752 regulates V_C to 12.8 V while in Sleep Mode to regulate the brightness of the Sleep-Mode LED. The Sleep Mode output voltage is high enough to drive at least three LED’s in series when additional brightness is required. This reduces the required value of R_LED and associated power consumption for a given LED bias current.

WAKE (TPS23752 only): The WAKE pin performs several functions. During Sleep Mode, it outputs a current-limited 2.5 V. Pushing the external pushbutton (S_WAKE in Figure 31) during Sleep Mode connects the WAKE pin to optocoupler, OPTO6. An internal current comparator detects this excess current drawn by OPTO6 and re-enables the DC-DC converter out of Sleep Mode. The WAKE pin now connects back to the internal pullup resistor (R_WKPLUP in the Sleep Mode block diagram) to provide bias current for OPTO6. The optocoupler alerts the system controller that the button has been pressed during sleep operation. Circuit board routing should protect WAKE from noise sources on the board.