SLVSB97E July   2012  – January 2018 TPS23751 , TPS23752

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1. 3.1 Typical Application Circuit
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings: Surge
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electric Characteristics - Controller Section
    7. 6.7 Electrical Characteristics - Sleep Mode (TPS23752 Only)
    8. 6.8 Electrical Characteristics - PoE Interface Section
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Pin Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 PoE Overview
        1. 7.4.1.1 Threshold Voltages
        2. 7.4.1.2 PoE Startup Sequence
        3. 7.4.1.3 Detection
        4. 7.4.1.4 Hardware Classification
        5. 7.4.1.5 Inrush and Startup
        6. 7.4.1.6 Maintain Power Signature
        7. 7.4.1.7 Startup and Converter Operation
        8. 7.4.1.8 PD Hotswap Operation
      2. 7.4.2 Sleep Mode Operation (TPS23752 only)
        1. 7.4.2.1  Converter Controller Features
        2. 7.4.2.2  PWM and VFO Operation; CTL, SRT, and SRD Pin Relationships to Output Load Current
        3. 7.4.2.3  Bootstrap Topology
        4. 7.4.2.4  Current Slope Compensation and Current Limit
        5. 7.4.2.5  RT
        6. 7.4.2.6  T2P, Startup and Power Management
        7. 7.4.2.7  Thermal Shutdown
        8. 7.4.2.8  Adapter ORing
        9. 7.4.2.9  Using DEN to Disable PoE
        10. 7.4.2.10 ORing Challenges
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistor, RCLS
        6. 8.2.2.6  APD Pin Divider Network, RAPD1, RAPD2
        7. 8.2.2.7  Setting the PWM-VFO Threshold using the SRT pin
        8. 8.2.2.8  Setting Frequency (RT)
        9. 8.2.2.9  Current Slope Compensation
        10. 8.2.2.10 Voltage Feed-Forward Compensation
        11. 8.2.2.11 Estimating Bias Supply Requirements and Cvc
        12. 8.2.2.12 Switching Transformer Considerations and RVC
        13. 8.2.2.13 T2P Pin Interface
        14. 8.2.2.14 Softstart
        15. 8.2.2.15 Special Switching MOSFET Considerations
        16. 8.2.2.16 ESD
        17. 8.2.2.17 Thermal Considerations and OTSD
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 PoE Overview

The following text is intended as an aid in understanding the operation of the TPS23751 and TPS23752 but not as a substitute for the IEEE 802.3at standard. The IEEE 802.3at standard is an update to IEEE 802.3-2008 clause 33 (PoE), adding high-power options and enhanced classification. Generally speaking, a device compliant to IEEE 802.3-2008 is referred to as a type 1 device, and devices with high power and enhanced classification are referred to as type 2 devices. Standards change and should always be referenced when making design decisions.

The IEEE 802.3at standard defines a method of safely powering a PD (powered device) over a cable by power sourcing equipment (PSE), and then removing power if a PD is disconnected. The process proceeds through an idle state and three operational states of detection, classification, and operation. The PSE leaves the cable unpowered (idle state) while it periodically looks to see if something has been plugged in; this operation is referred to as detection. The low power levels used during detection are unlikely to damage devices not designed for PoE. If a valid PD signature is present, the PSE may inquire how much power the PD requires; this operation is referred to as classification. The PSE may then power the PD if it has adequate capacity.

Type 2 PSEs are required to do type 1 hardware classification plus a (new) data-layer classification, or an enhanced type 2 hardware classification. Type 1 PSEs are not required to do hardware or data link layer (DLL) classification. A type 2 PD must do type 2 hardware classification as well as DLL classification. The PD may return the default, 13W current-encoded class, or one of four other choices. DLL classification occurs after power-on and the Ethernet data link has been established.

Once started, the PD must present a Maintain Power Signature (MPS) to assure the PSE that it is still present. The PSE monitors its output for a valid MPS and turns the port off if it loses the MPS. Loss of the MPS returns the PSE to the idle state. Figure 22 shows the operational states as a function of PD input voltage. The upper half is for IEEE 802.3-2008, and the lower half shows specific differences for IEEE 802.3at. The dashed lines in the lower half indicate these states are the same (e.g., Detect and Class) for both.

TPS23751 TPS23752 Thresh_Volt_01_SLVSB97.gifFigure 22. Threshold Voltages

The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD input requirements differ from PSE output requirements to account for voltage drops and operating margin. The standard allots the maximum loss to the cable regardless of the actual installation to simplify implementation. IEEE 802.3-2008 was designed to run over infrastructure including ISO/IEC 11801 class C (CAT3 per TIA/EIA-568) that may have had AWG 26 conductors. IEEE 802.3at type 2 cabling power loss allotments and voltage drops have been adjusted for 12.5 Ω power loops per ISO/IEC11801 class D (CAT5 or higher per TIA/EIA-568, typically AWG 24 conductors). Table 2 shows key operational limits broken out for the two revisions of the standard.

Table 2. Comparison of Operational Limits

StandardPower Loop Resistance
(max)		PSE Output
Power (min)		PSE Static Output
Voltage (min)		PD Input
Power (max)		Static PD Input Voltage
Power ≤ 12.95WPower > 12.95W
IEEE802.3at-2008
802.3at (Type 1)		 20 Ω 15.4W 44 V 12.95W 37 V – 57 V N/A
802.3at (Type 2) 12.5Ω 30W 50 V 25.5W 37 V – 57 V 42.5 V – 57 V

The PSE can apply voltage either between the RX and TX pairs (pins 1 - 2 and 3 - 6 for 10baseT or 100baseT), or between the two spare pairs (4 - 5 and 7 - 8). Power application to the same pin combinations in 1000baseT systems is recognized in IEEE 802.3at. 1000baseT systems can handle data on all pairs, eliminating the spare pair terminology. The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode bridges to accept power from any of the possible PSE configurations. The voltage drops associated with the input bridges create a difference between the standard limits at the PI and the TPS23751 and TPS23752 specifications.

A compliant type 2 PD has power management requirements not present with a type 1 PD. These requirements include the following:

  1. Must interpret type 2 hardware classification,
  2. Must present hardware class 4,
  3. Must implement DLL negotiation,
  4. Must behave like a type 1 PD during inrush and startup,
  5. Must not draw more than 13W for 80ms after the PSE applies operating voltage (power-up),
  6. Must not draw more than 13W if it has not received a type 2 hardware classification or received permission through DLL,
  7. Must meet various operating and transient templates, and
  8. Optionally monitor for the presence or absence of an adapter (assume high power).

As a result of these requirements, the PD must be able to dynamically control its loading, and monitor T2P for changes. In cases where the design needs to know specifically if an adapter is plugged in and operational, the adapter should be individually monitored, typically with an optocoupler.