SLVS728D January   2007  – October 2019 TPS2412 , TPS2413

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Definitions
      2. 8.3.2 TPS2412 vs TPS2413 – MOSFET Control Methods
      3. 8.3.3 N+1 Power Supply – Typical Connection
      4. 8.3.4 Input ORing – Typical Connection
      5. 8.3.5 System Design and Behavior With Transients
      6. 8.3.6 TPS2412 Regulation-Loop Stability
      7. 8.3.7 MOSFET Selection and R(RSET)
      8. 8.3.8 Gate Drive, Charge Pump and C(BYP)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Recommended Operating Range
    2. 10.2 VDD, BYP, and Powering Options
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • PW|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.2 VDD, BYP, and Powering Options

The separate VDD pin provides flexibility for operational power and controlled rail voltage. While the internal UVLO has been set to 2.5 V, the TPS2412/13 requires at least 3 V to generate the specified GATE drive voltage. Sufficient BYP voltage to run internal circuits occurs at VDD voltages from 2.5 V to 3 V. There are three choices for power, A, C, or a separate supply, two of which are demonstrated in Figure 14. One choice for voltage rails over 3.3 V is to power from C, because it is typically the source of reliable power. Voltage rails below 3.3 V nominal, for example, 2.5 V and below, should use a separate supply such as 5 V. A separate VDD supply can be used to control voltages above it, for example 5 V powering VDD to control a 12-V bus.

VDD is the main source of power for the internal control circuits. The charge pump that powers BYP draws most of its power from VDD. The input should be low impedance, making a bypass capacitor a preferred solution. A 10-Ω series resistor may be used to limit inrush current into the bypass capacitor, and to provide noise filtering for the supply.

BYP is the interconnection point between a charge pump, V(AC) monitor amplifiers and comparators, and the gate driver. C(BYP) must be used to filter the charge pump. A 2200 pF is recommended, but the value is not critical.

TPS2412 TPS2413 vdd_pwr_exm_lvs727.gifFigure 14. VDD Powering Examples