SLVSAL1E March   2011  – April 2016 TPS24720

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 THERMAL INFORMATION
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Descriptions
        1. 7.3.1.1  EN
        2. 7.3.1.2  ENSD
        3. 7.3.1.3  FFLTb
        4. 7.3.1.4  FLTb
        5. 7.3.1.5  GATE
        6. 7.3.1.6  GND
        7. 7.3.1.7  IMON
        8. 7.3.1.8  LATCH
        9. 7.3.1.9  OUT
        10. 7.3.1.10 OV
        11. 7.3.1.11 PGb
        12. 7.3.1.12 PROG
        13. 7.3.1.13 SENSE
        14. 7.3.1.14 SET
        15. 7.3.1.15 TIMER
        16. 7.3.1.16 VCC
    4. 7.4 Device Functional Modes
      1. 7.4.1  Board Plug-In
      2. 7.4.2  Inrush Operation
      3. 7.4.3  Action of the Constant-Power Engine
      4. 7.4.4  Circuit Breaker and Fast Trip
      5. 7.4.5  Automatic Restart
      6. 7.4.6  PGb, FLTb, and Timer Operations
      7. 7.4.7  Overtemperature Shutdown
      8. 7.4.8  Start-Up of Hot-Swap Circuit by VCC or EN
      9. 7.4.9  Minimization of Power Dissipation at STANDY by ENSD
      10. 7.4.10 Fault Detection of MOSFET Short With FFLTb
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power-Limited Start-Up
          1. 8.2.2.1.1 STEP 1. Choose RSENSE, RSET, and RIMON
          2. 8.2.2.1.2 STEP 2. Choose MOSFET M1
          3. 8.2.2.1.3 STEP 3. Choose Power-Limit Value, PLIM, and RPROG
          4. 8.2.2.1.4 STEP 4. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT
          5. 8.2.2.1.5 STEP 5. Calculate the Retry-Mode Duty Ratio
          6. 8.2.2.1.6 STEP 6. Select R1, R2, and R3 for UV and OV
          7. 8.2.2.1.7 STEP 7. Choose RGATE, R4, R5, R6, and C1
        2. 8.2.2.2 Additional Design Considerations
          1. 8.2.2.2.1 Use of PGb
          2. 8.2.2.2.2 Output Clamp Diode
          3. 8.2.2.2.3 Gate Clamp Diode
          4. 8.2.2.2.4 High-Gate-Capacitance Applications
          5. 8.2.2.2.5 Bypass Capacitors
          6. 8.2.2.2.6 Output Short-Circuit Measurements
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS24720 is a hotswap used to manage inrush current and provide load fault protection. When designing a hotswap, three key scenarios should be considered:

  • Start-up
  • Output of a hotswap is shorted to ground when the hotswap is on. This is often referred to as a hot-short.
  • Powering-up a board when the output and ground are shorted. This is usually called a start-into-short.

Each of these scenarios place stress on the hotswap MOSFET. Take special care when designing the hotswap circuit to keep the MOSFET within its SOA. The following design example is provided as a guide. Use the TPS24720 Design Calculator (SLVC563) to assist with the detailed design equation calculations.

8.2 Typical Application

This section provides an application example utilizing power limited start-up and MOSFET SOA protection. The design parameters are listed in the Design Requirements section and represent a more moderate level of fault current. For more stringent current levels, refer to either the TPS24720EVM (SLUU458) (25 A design) or the calculator tool (SLVC563) (50 A design).

TPS24720 fp_schematic_slvsal1.gif Figure 37. Typical Application (12 V at 10 A)

8.2.1 Design Requirements

For this design example, use the parameters shown in Table 1.

Table 1. Design Parameters

PARAMETER VALUE
Input voltage 12 V ±2V
Maximum operating load current 10 A
Operating temperature 20°C —50°C
Fault trip current 12 A
Load capacitance 470 µF

8.2.2 Detailed Design Procedure

8.2.2.1 Power-Limited Start-Up

This design example assumes a 12-V system voltage with an operating tolerance of ±2 V. The rated load current is 10 A, corresponding to a dc load of 1.2 Ω. If the current exceeds 12 A, then the controller should shut down and then attempt to restart. Ambient temperatures may range from 20°C to 50°C. The load has a minimum input capacitance of 470 μF. Figure 38 shows a simplified system block diagram of the proposed application.

This design procedure seeks to control the junction temperature of MOSFET M1 under both static and transient conditions by proper selection of package, cooling, rDS(on), current limit, fault timeout, and power limit. The design procedure further assumes that a unit running at full load and maximum ambient temperature experiences a brief input power interruption sufficient to discharge COUT, but short enough to keep M1 from cooling. A full COUT recharge then takes place. Adjust this procedure to fit the application and design criteria.

TPS24720 B0440-01_LVSAL1.gif Figure 38. Simplified Block Diagram of the System Constructed in the Design Example

8.2.2.1.1 STEP 1. Choose RSENSE, RSET, and RIMON

The recommended range of the current-limit threshold voltage, V(VCC – SENSE), extends from 10 mV to 42 mV. Values near the low threshold of 10 mV may be affected by system noise. Values near the upper threshold of 42 mV may be too close to the minimum fast-trip threshold voltage of 52 mV. Values near the middle of this range help minimize both concerns.

To achieve high efficiency, the power dissipation in RSENSE must be kept to a minimum. A RSENSE of 2 mΩ develops a voltage of 24 mV at the specified peak current limit of 12 A, while dissipating only 200 mW at the rated 10-A current. This represents a 0.17% power loss.

For best performance, a current of approximately 0.5 mA (referring to the RECOMMENDED OPERATING CONDITIONS table) should flow into the SET pin and out of the IMON pin when the TPS24720 is in current limit. The voltage across RSET nominally equals the voltage across RSENSE, or 24 mV. Dividing 24 mV by 0.5 mA gives a recommended value of RSET of 48 Ω. A 51.1-Ω, 1% resistor was chosen. Using Equation 3, the value of RIMON must equal 1437 Ω, or as near as practically possible. A 1.43-kΩ, 1% resistor was chosen.

Equation 5. TPS24720 EQ_Rimon_LVSAL1.gif

8.2.2.1.2 STEP 2. Choose MOSFET M1

The next design step is to select M1. The TPS24720 is designed to use an N-channel MOSFET with a gate-to-source voltage rating of 20 V.

Devices with lower gate-to-source voltage ratings can be used if a Zener diode is connected so as to limit the maximum gate-to-source voltage the transistor sees.

The next factor to consider is the drain-to-source voltage rating, VDS(MAX), of the MOSFET. Although the MOSFET only sees 12 V dc, it may experience much higher transient voltages during extreme conditions, such as the abrupt shutoff that occurs during a fast trip. A TVS may be required to limit inductive transients under such conditions. A transistor with a VDS(MAX) rating of at least twice the nominal input power-supply voltage is recommended regardless of whether a TVS is used or not.

Next select the on-resistance of the transistor, rDS(on). The maximum on-resistance must not generate a voltage greater then the minimum power-good threshold voltage of 140 mV. Assuming a current limit of 12 A, a maximum rDS(on) of 11.67 mΩ is required. Also consider the effect of rDS(on) on the maximum operating temperature TJ(MAX) of the MOSFET. Equation 6 computes the value of rDS(on)(MAX) at a junction temperature of TJ(MAX). Most manufacturers list rDS(on)(MAX) at 25°C and provide a derating curve from which values at other temperatures can be derived. Compute the maximum allowable on-resistance, rDS(on)(MAX), using Equation 6.

Equation 6. TPS24720 EQ_rDSon_LVSAL1.gif

Taking these factors into consideration, the TI CSD16403Q5 was selected for this example. This transistor has a VGS(MAX) rating of 16 V, a VDS(MAX) rating of 25 V, and a maximum rDS(on) of 2.8 mΩ at room temperature. During normal circuit operation, the MOSFET can have up to 10 A flowing through it. The power dissipation of the MOSFET equates to 0.24 W and an 9.6°C rise in junction temperature. This is well within the data sheet limits for the MOSFET. The power dissipated during a fault (e.g., output short) is far larger than the steady-state power. The power handling capability of the MOSFET must be checked during fault conditions.

8.2.2.1.3 STEP 3. Choose Power-Limit Value, PLIM, and RPROG

MOSFET M1 dissipates large amounts of power during inrush. The power limit PLIM of the TPS24720 should be set to prevent the die temperature from exceeding a short-term maximum temperature, TJ(MAX)2. The short-term TJ(MAX)2 could be set as high as 150°C while still leaving ample margin to the usual manufacturer’s rating of 175°C. Equation 7 is an expression for calculating PLIM,

Equation 7. TPS24720 EQ_Plim_3_LVSAL1.gif

where RθJC is the junction-to-case thermal resistance of the MOSFET, rDS(on) is the its resistance at the maximum operating temperature, and the factor of 0.8 represents the tolerance of the constant-power engine. For an ambient temperature of 50°C, the calculated maximum PLIM is 29.3 W. From Equation 1, a 53.6-kΩ, 1% resistor is selected for RPROG (see Equation 8).

Equation 8. TPS24720 EQ_Rprog_LVSAL1.gif

Power limit fold back (PLIM-FB) is the ratio of operating current limit (ILIM) and minimum power limited (regulated) current (when VOUT = 0 V). Degradation of programmed power limit (PLIM) accuracy and start up issues may occur if PLIM-FB is too large. Equation 9 calculates VSNS-PL_MIN (minimum sense voltage during power limit) and PLIM-FB. To ensure reliable operation, verify that PLIM-FB < 10 and VSNS,PL,MIN > 3 mV.

Equation 9. TPS24720 EQ_Vsns_LVSAL1.gif

8.2.2.1.4 STEP 4. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT

The maximum output voltage rise time, tON, set by timer capacitor CT must suffice to fully charge the load capacitance COUT without triggering the fault circuitry. Equation 10 defines tON for two possible inrush cases. Assuming that only the load capacitance draws current during startup,

Equation 10. TPS24720 EQ_tON_LVSAL1.gif

The next step is to determine the minimum fault-timer period. In Equation 10, the output rise time is tON. This is the amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer uses the difference between the input voltage and the gate voltage to determine if the TPS24720 is still in inrush limit. The fault timer continues to run until VGS rises 5.9 V (for VVCC = 12 V) above the input voltage. Some additional time must be added to the charge time to account for this additional gate voltage rise. The minimum fault time can be calculated using Equation 11,

Equation 11. TPS24720 EQ_tFLT_LVSAL1.gif

where CISS is the MOSFET input capacitance and IGATE is the minimum gate sourcing current of TPS24720, or 20 μA. Using the example parameters and the CSD16403Q5 data sheet in Equation 11 leads to a minimum fault time of 1.22 ms. This time is derived considering the tolerances of COUT, CISS, ILIM, PLIM, IGATE, and VVCC(MAX). The fault timer must be set to a value higher than 1.22 ms to avoid turning off during start-up, but lower than any maximum fault time limit determined by the device SOA curve (see Figure 39) derated for operating junction temperature.

For this example, select 7 ms to allow for variation of system parameters such as temperature, load, component tolerance, and input voltage. The timing capacitor is calculated in Equation 12 as 52 nF. Selecting the next-highest standard value, 56 nF, yields a 7.56-ms fault time.

Equation 12. TPS24720 EQ_Ct_2_LVSAL1.gif

8.2.2.1.5 STEP 5. Calculate the Retry-Mode Duty Ratio

In retry mode, the TPS24720 is on for one charging cycle and off for 16 charge/discharge cycles, as can be seen in Figure 35. The first CT charging cycle is from 0 V to 1.35 V, which gives 7.56 ms. The first CT discharging cycle is from 1.35 V to 0.35 V, which gives 5.6 ms. Therefore, the total time is 7.56 ms + 33 x 5.6 ms = 192.36 ms. As a result, the retry mode duty ratio is 7.56 ms/192.36 ms = 3.93%.

8.2.2.1.6 STEP 6. Select R1, R2, and R3 for UV and OV

Next, select the values of the OV and UV resistors, R1, R2, and R3, as shown in the typical application diagram on the front page. From the TPS24720 electrical specifications, VOVTHRESH = 1.35 V and VENTHRESH = 1.35 V. VOV is the overvoltage trip voltage, which in this case is 14 V. VUV is the undervoltage trip voltage, which for this example equals 10.8 V.

Equation 13. TPS24720 EQ_Vent_LVSAL1.gif
Equation 14. TPS24720 EQ_Vuvt_LVSAL1.gif

Assume R3 is 1 kΩ and use Equation 13 to solve for (R2 + R3). Use Equation 14 and the (R2 + R3) from Equation 13 to solve for R2 and finally for R3. From Equation 13, (R2 + R3) = 9370.4 Ω. From Equation 14,
R2 = 296 Ω and R1 = 9.074 kΩ. Scaling all three resistors by a factor of ten to use less supply current for these voltage references and using standard 1% resistor values gives R1 = 90.9 kΩ, R2 = 2.94 kΩ, and R3 = 10 kΩ.

8.2.2.1.7 STEP 7. Choose RGATE, R4, R5, R6, and C1

In the typical application diagram on the front page, the gate resistor, RGATE, is intended to suppress high-frequency oscillations. A resistor of 10 Ω serves for most applications, but if M1 has a CISS below 200 pF, then 33 Ω is recommended. Applications with larger MOSFETs and very short wiring may not require RGATE. R4, R5, and R6 are required only if PGb, FLTb, and FFLTb are used; these resistors serve as pullups for the open-drain output drivers. The current sunk by each of these pins should not exceed 2 mA ( referring to the Recommended Operating Conditions). C1 is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise while in the disabled state. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended.

8.2.2.2 Additional Design Considerations

8.2.2.2.1 Use of PGb

Use the PGb pin to control and coordinate a downstream dc/dc converter. If this is not done, then a long time delay is needed to allow COUT to fully charge before the converter starts. An undesirable latch-up condition can be created between the TPS24720 output characteristic and the dc/dc converter input characteristic if the converter starts while COUT is still charging; using the PGb pin is one way to avoid this.

8.2.2.2.2 Output Clamp Diode

Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a current-limit event. The OUT pin ratings can be satisfied by connecting a diode from OUT to GND. The diode should be selected to control the negative voltage at the full short-circuit current. Schottky diodes are generally recommended for this application.

8.2.2.2.3 Gate Clamp Diode

The TPS24720 has a relatively well-regulated gate voltage of 12 V–15.5 V with a supply voltage VVCC higher than 4 V. A small clamp Zener from gate to source of M1 is recommended if VGS of M1 is rated below 12 V. A series resistance of several hundred ohms or a series silicon diode is recommended to prevent the output capacitance from discharging through the gate driver to ground.

8.2.2.2.4 High-Gate-Capacitance Applications

Gate voltage overstress and abnormally large fault-current spikes can be caused by large gate capacitance. An external gate clamp Zener diode is recommended to assist the internal Zener if the total gate capacitance of M1 exceeds about 4000 pF.

8.2.2.2.5 Bypass Capacitors

It is a good practice to provide low-impedance ceramic capacitor bypassing of the VCC and OUT pins. Values in the range of 10 nF to 1 µF are recommended. Some system topologies are insensitive to the values of these capacitors; however, some are not and require minimization of the value of the bypass capacitor. Input capacitance on a plug-in board may cause a large inrush current as the capacitor charges through the low-impedance power bus when inserted. This stresses the connector contacts and causes a short voltage sag on the input bus. Small amounts of capacitance (e.g., 10 nF to 0.1 µF) are often tolerable in these systems.

8.2.2.2.6 Output Short-Circuit Measurements

Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads, circuit layout and component selection, output shorting method, relative location of the short, and instrumentation all contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do not expect to see waveforms exactly like those in the data sheet; every setup differs.

8.2.3 Application Curve

TPS24720 G009_LVSAL2.gif Figure 39. CSD16403Q5 SOA Curve