The TPS2474x is an integrated ORing and Hot Swap controller for 2.5 V to 18 V systems. It's precise and programmable protection settings aid in the design of high power, high availability systems where isolating faults is critical.
Programmable current limit, fast shut down, and fault timer protect the load and supply during fault conditions such as a hot - short. The fast shutdown threshold and response time can be tuned to ensure a fast response to real faults, while avoiding nuisance trips. Programmable SOA (Safe Operating Area) protection and the inrush timer keep the MOSFET safe under all operating conditions. After asserting a power good, TPS2474x runs the fault timer during over-current events, but doesn't current limit. It shuts down after the fault timer expires. Two independent timers (inrush/fault) allow the user to customize protection based on system requirements. The ORing function of the TPS2474x allows the user to program the reverse voltage threshold and response time to aid in the design of redundant power supply systems.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS24740 TPS24741 TPS24742 |
VQFN (24) | 4.00 mm x 4.00 mm |
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TPS2474x in Priority Muxing![]() |
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Changes from * Revision (January 2015) to A Revision
PART NUMBER(1) | LATCH / RETRY OPTION |
---|---|
TPS24740 | Latch |
TPS24741 | Auto – Retry |
TPS24742 | Fast Latch Off |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
A | 23 | I/P | Voltage sense input that connects to the OR MOSFET's body diode's anode. Connect to the OR MOSFET source in the typical configuration. A pin is used to supply power to the ORing block of the TPS2474x under certain biasing conditions. |
BGATE | 22 | O | Connect to the gate of the external OR MOSFET. Controls the OR MOSFET to emulate a low forward-voltage diode. |
C | 20 | I/P | Voltage sense input that connects to the OR MOSFET's body diode's cathode. Connect to the OR MOSFET drain in the typical configuration. C pin is used to supply power to the ORing block of the TPS2474x under certain biasing conditions. |
CP | 1 | I/O | Connect a storage capacitor from CP to A for fast turn-on of blocking Gate. |
ENHS | 2 | I | Active-high enable input of Hot-swap. Logic input. Connects to resistor divider. |
ENOR | 3 | I | Active-high enable input of Oring. Logic input. Connects to resistor divider. |
FLTb | 4 | O | Active-low, open-drain output indicating various faults. |
FSTP | 16 | I | Fast trip programming set pin for hot-swap. Connect RFSTP from the positive terminal of the Hot Swap sense resistor to the FSTP pin. |
GND | 10 | – | Ground. |
HGATE | 18 | O | Gate driver output for external Hot Swap MOSFET. |
IMON | 12 | I/O | Analog current monitor and load current limit program point. Connect RIMON to ground. |
IMONBUF | 13 | O | Voltage output proportional to the load current (0V–3.0V). |
OUTH | 19 | I | Output voltage sensor for monitoring Hot Swap MOSFET power. Connects to the source terminal of the hot-swap N channel MOSFET. |
OV | 9 | I | Overvoltage comparator input. Connects to resistor divider. HGATE and BGATE are pulled low when OV exceeds the threshold. Connect to ground when not used. |
PGHS | 5 | O | Active-high, open-drain power-good indicator. |
PLIM | 11 | I | Power-limiting programming pin. A resistor from this pin to GND sets the maximum power dissipation for the Hot Swap FET. |
RVSNP | 21 | I | Positive input of the reverse voltage comparator. Connect a resistor from RVSNP to C to set the reverse voltage trip point of the blocking FET. |
RVSNM | 24 | I | Negative input of the reverse voltage comparator. |
SENM | 17 | I | Current-sensing input for the sensing resistor. Directly connects to the negative terminal of the sensing resistor. |
SET | 15 | I | Current-limit programming set pin for hot-swap. A resistor is connected from positive terminal of the sensing resistor. |
STAT | 6 | O | High when BGATE is ON. |
TFLT | 8 | I/O | Fault timer, which runs when the device goes from regular operation to an over-current condition. |
TINR | 7 | I/O | Inrush timer, which runs during the inrush operation (start-up) if the part is in current limit or power limit. |
VDD | 14 | P | Power Supply. |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD)(1) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2) | ±1500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(3) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VDD, SENM, SET(1), FSTP | 2.5 | 18 | V |
ENHS, ENOR, FLTb, PGHS, STAT, OUTH | 0 | 18 | ||
A, C, RVSNM, RVSNP; (2) | 0.7 | 18 | ||
Sink current | FLTb, PGHS, STAT | 0 | 2 | mA |
Source current | IMON | 0 | 1 | mA |
External resistance | PLIM | 4.99 | 500 | kΩ |
IMON | 1 | 6 | kΩ | |
RVSNP | 10 | 1000 | Ω | |
FSTP | 10 | 4000 | Ω | |
SET | 10 | 400 | Ω | |
RIMON / RSET | w/o RSTBL(4) | 10 | 70 | |
With appropriate RSTBL | 3 | 10 | ||
External capacitor | CP, FSTP, RVSNP | 1 | 1000 | nF |
HGATE, BGATE (3) | 0 | 1 | µF | |
TINR, TFLT | 1 | nF | ||
IMON | 30 | pF | ||
IMONBUF | 100 | pF | ||
Operating junction temperature, TJ | –40 | 125 | °C |
THERMAL METRIC(1) | TPS24740, TPS24741, TPS24742 | UNIT | |
---|---|---|---|
RGE (24 PINS) | |||
RθJA | Junction-to-ambient thermal resistance | 34.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 38.4 | |
RθJB | Junction-to-board thermal resistance | 12.9 | |
ψJT | Junction-to-top characterization parameter | 0.5 | |
ψJB | Junction-to-board characterization parameter | 12.9 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.2 |
PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT SUPPLY (VDD) | ||||||
VUVR | UVLO threshold, rising | 2.2 | 2.32 | 2.45 | V | |
VUVhyst | UVLO hysteresis | 0.1 | V | |||
IQON | Supply current: IVDD+IA+IC+ IOUTH | Device on, VENHS = VENOR = 2V | 4.2 | 6 | mA | |
HOT SWAP FET ENABLE (ENHS) | ||||||
VENHS | Threshold voltage, rising | 1.3 | 1.35 | 1.4 | V | |
VENHShyst | Hysteresis | 50 | mV | |||
IENHS | Input Leakage Current | 0 ≤ VENHS ≤ 30V | –1 | 1 | µA | |
BLOCKING (ORING) FET ENABLE (ENOR) | ||||||
VENOR | Threshold voltage, rising | 1.3 | 1.35 | 1.4 | V | |
VENORhyst | Hysteresis | 50 | mV | |||
IENOR | Input leakage current | 0 V ≤ VENOR ≤ 30V | –1 | 0 | 1 | µA |
OVER VOLTAGE (OV) | ||||||
VOVR | Threshold voltage, rising | 1.3 | 1.35 | 1.4 | mV | |
VOVhyst | Hysteresis | 50 | mV | |||
IOV | Input leakage current | 0 ≤ VOV ≤ 30V | –1 | 1 | µA | |
POWER LIMIT PROGRAMING (PLIM) | ||||||
VPLIM,BIAS | Bias voltage | Sourcing 10μA | 0.66 | 0.675 | 0.69 | V |
VIMON,PL | Regulated IMON voltage during power limit | RPLIM = 52 kΩ; VSENM-OUTH=12V; | 114.75 | 135 | 155.25 | mV |
RPLIM = 105 kΩ; VSENM-OUTH=12V; | 56.95 | 67 | 77.05 | |||
RPLIM = 261 kΩ; VSENM-OUTH=12V; | 18.9 | 27 | 35.1 | |||
RPLIM = 105 kΩ; VSENM-OUTH=2V; | 341.7 | 402 | 462.3 | |||
RPLIM = 105 kΩ; VSENM-OUTH=18V; | 38.25 | 45 | 51.75 | |||
SLOW TRIP THRESHOLD (SET) | ||||||
VOS_SET | Input referred offset (VSNS to VIMON scaling) | RSET = 44.2Ω; RIMON=3kΩ to 1.2kΩ (corresponds to VSNS,CL=10mV to 25mV) | –150 | 150 | µV | |
VGE_SET | Gain error (VSNS to VIMON scaling)(1) | –0.4% | 0.4% | |||
FAST TRIP THRESHOLD PROGRAMMING (FSTP) | ||||||
IFSTP | FSTP input bias current | VFSTP=12V | 95 | 100 | 105 | µA |
VFASTRIP | Fast trip threshold | RFSTP = 200 Ω, VSNS when VHGATE ↓ | 18 | 20 | 22 | mV |
RFSTP = 1 kΩ, VSNS when VHGATE ↓ | 95 | 100 | 105 | |||
RFSTP = 4 kΩ, VSNS when VHGATE ↓ | 380 | 400 | 420 | |||
CURRENT MONITOR and CURRENT LIMIT PROGRAMING (IMON) | ||||||
VIMON,CL | Slow trip threshold at summing node | VIMON↑, when ITFLT starts sourcing | 660 | 675 | 690 | mV |
CURRENT MONITOR (IMONBUF) | ||||||
VOS_IMONBUF | Buffer offset | VIMON = 50mV to 675mV, Input referred | –3 | 0 | 3 | mV |
GAINIMONBUF | Buffer voltage gain | ΔVIMONBUFF / ΔVIMON | 2.97 | 2.99 | 3.01 | V |
BWIMONBUF | Buffer closed loop bandwidth | CIMONBUF = 75pF | 1 | MHz | ||
HOT SWAP GATE DRIVER (HGATE) | ||||||
VHGATE | HGATE output voltage | 5 ≤ VVDD ≤ 16V; measure VHGATE-OUTH | 12 | 13.6 | 15.5 | V |
2.5V <VVDD < 5V; 16V <VVDD < 20V measure VHGATE-OUTH |
7 | 7.95 | 15 | V | ||
VHGATEmax | Clamp voltage | Inject 10μA into HGATE, measure V(HGATE – OUTH) | 12 | 13.9 | 15.5 | V |
IHGATEsrc | Sourcing current | VHGAT-OUTH = 2V-10V | 44 | 55 | 66 | µA |
IHGATEfastSink | Sinking current for fast trip | VHGATE-OUTH = 2V -15V; V(FSTP – SENM) = 20mV | 0.45 | 1 | 1.6 | A |
IHGATEsustSink | Sustained sinking current | Sustained, VHGATE-OUTH = 2V – 15V; VENHS = 0 | 30 | 44 | 60 | mA |
CURRENT SENSE NEGATIVE INPUT (SENM) | ||||||
ISENM | Input bias current | VSENM = 12V | 15 | 20 | µA | |
INRUSH TIMER (TINR) | ||||||
ITINRsrc | Sourcing current | VTINR = 0V, In power limit or current limit | 8 | 10.25 | 12.5 | µA |
ITINRsink | Sinking current | VTINR = 2V, In regular operation | 1.5 | 2 | 2.5 | µA |
VTINRup | Upper threshold voltage | Raise VTINR until HGATE starts sinking | 1.3 | 1.35 | 1.4 | V |
VTINRlr | Lower threshold voltage | Raise VTINR to 2V. Reduce VTINR until ITINR is sourcing. | 0.33 | 0.35 | 0.37 | v |
RTINR | Bleed down resistance | VVDD = 0V, VTINR = 2V | 70 | 104 | 130 | kΩ |
ITINR-PD | Pulldown current | VTINR = 2V, when VENHS = 0V | 2 | 4.2 | 7 | mA |
VIMON,TINR | See (2) | RPLIM = 52kΩ, VSENM = 12V, VOUTH = 0 V. Raise IMON voltage and record IMON when TINR starts sourcing current | 47.75 | 90 | 132.25 | mV |
VIMON,PL | See (2) | RPLIM = 52kΩ, VSENM = 12V, VOUTH = 0 V. Raise IMON voltage and record IMON when IHGATE starts sinking current. | 114.75 | 135 | 155.25 | mV |
ΔVIMON,TINR | See (2) | RPLIM = 52kΩ, VSENM = 12V, VOUTH = 0 V. ΔVIMON,TINR = VIMON,PL – VIMON,TINR |
23 | 45 | 67 | mV |
FAULT TIMER (TFLT) | ||||||
ITFLTsrc | Sourcing current | VTFLT = 0V, PGHS is high and in overcurrent | 8 | 10.25 | 12.5 | µA |
ITFLTsink | Sinking current | VTFLT = 2V, Not in overcurrent | 1.5 | 2 | 2.5 | µA |
VTFLTup | Upper threshold voltage | Raise VTFLT until HGATE starts sinking | 1.3 | 1.35 | 1.4 | V |
RTFLT | Bleed down resistance | VVDD = 0V, VTFLT = 2V | 70 | 104 | 130 | kΩ |
ITFLT-PD | Pulldown current | VTFLT = 2V, when VENHS = 0V | 2 | 5.6 | 7 | mA |
HOT SWAP OUTPUT (OUTH) | ||||||
IOUTH, BIAS | Input bias current | VOUTH = 12V | 30 | 70 | µA | |
CHARGE PUMP FOR BGATE (CP) | ||||||
ICP | CP Equivalent charging resistance | VA = 12 V , 1mA CP current | 5 | 8.7 | 12.5 | kΩ |
VCP | CP Output voltage | Max(VA, VC, VVDD) > 6 V, Measure VCP-A | 9 | 10 | 11 | V |
6V > Max(VA, VC, VVDD) > 4V, Measure VCP-A | 5 | 5.9 | 11 | |||
Max(VA, VC, VVDD) = 2.5 V, Measure VCP-A | 8 | 9.8 | 11 | |||
BLOCKING/ORING GATE DRIVER (BGATE) | ||||||
IBGATE_CHRG | BGATE Pull up current | VAC = 20mV, pulse | 30 | mA | ||
VAC = 20mV, sustained | 0.2 | 0.3 | 0.4 | mA | ||
IBGATEsustSink | BGATE Sinking current | Fast turnoff, VBGATE-A = 7V | 0.4 | 0.9 | 1.4 | A |
Sustained, VBGATE-A = 2V to 11V | 19 | 35 | 65 | mA | ||
BLOCKING/ORing ANODE (A) | ||||||
IA | Input current(3) | 2.5 V ≤ VA ≤ 18V | 3 | mA | ||
VA_UVLO | Undervoltage lockout | VA increasing and VVDD=VC=0.7V | 1.85 | 1.93 | 2.05 | V |
VA_UVLO_hyst | Undervoltage lockout hysteresis | 0.1 | V | |||
BLOCKING/ORing CATHODE (C) | ||||||
IC | Input current(3) | 2.5 V ≤ VC ≤ 18V | 3 | mA | ||
VC_UVLO | Undervoltage lockout | VC increasing and VDD=VA=0.7V | 1.85 | 1.93 | 2.05 | V |
VC_UVHyst | Hysteresis | 100 | mV | |||
VFWDTH | Forward turn-on voltage | Measure VAC when VBGATE ↑ | 7.5 | 10 | 12.5 | mV |
POSITIVE INPUT OF REVERSE VOLTAGE COMPARATOR (RVSNP) | ||||||
IRVSNP | RVSNP Input bias current | VRVSNP = 12V, sinking current; 0.7V < VA, VRVSNM < 20V |
93 | 99 | 105 | µA |
VRVTRIP1 | Reverse Comparator Offset | RRV=10Ω, Measure VRVSNP-RVSNM, when BGATE↓ | -1 | 0 | 1 | mV |
NEGATIVE INPUT OF REVERSE VOLTAGE COMPARATOR (RVSNM) | ||||||
IRVSNM | Leakage current | –2 | 2 | µA | ||
FAULT INDICATOR (FLTb) | ||||||
VOL_FLTb | Output low voltage | Sinking 2 mA | 0.11 | 0.25 | V | |
IFLTb | Input Leakage Current | VFLTb = 0V, 30V | –1 | 0 | 1 | µA |
VHSFLT_IMON | VIMON threshold to detect Hot Swap FET short | VENHS = 0V, Measured VIMON ↑ to GND when FLTb ↓ | 88 | 101 | 115 | mV |
VHSFL_hyst | Hysteresis | 25 | mV | |||
VBFET, OPEN, FLT | A-C threshold to detect OPEN Blocking/ORing FET fault | VENOR=3V, Measure VA-C to FLTb↓, VCP-A > 7V | 350 | 410 | 490 | mV |
VCP_FLT | CP fault threshold | Measure VCP-A ↓ when FLTb↓, 4V ≤ VVDD < 18V | 5 | 5.5 | 6 | V |
Measure VCP-A ↓ when FLTb↓, 2.5V < VVDD < 4V | 3.3 | 3.75 | 4.2 | V | ||
VCP, FLT, hyst | Hysteresis | 4V ≤ VVDD < 18V | 1.5 | V | ||
2.5V < VVDD < 4V | 1.1 | V | ||||
HOT SWAP POWER GOOD OUTPUT (PGHS) | ||||||
VPGHSth | PGHS Threshold | Measure VSENM-OUTH ↓ when PGHS↑ | 170 | 270 | 375 | mV |
VPGHShyst | PGHS hysteresis | VSENM-OUTH ↑ | 80 | mV | ||
VOL_PGHS | PGHS Output low voltage | Sinking 2mA | 0.11 | 0.25 | V | |
IPGHS | PHGS Input leakage current | VPGHS=0V to 30V | –1 | 0 | 1 | µA |
STATUS INDICATOR (STAT) | ||||||
VSTATon | Status ON threshold | 4V ≤ VVDD < 20V , Measure VBGATE – A ↑, when STAT↑ | 5 | 6 | 7 | V |
2.5V < VVDD < 4V , Measure VBGATE – A ↑, when STAT↑ | 3.6 | 4 | 4.4 | V | ||
VSTAToff | Status OFF threshold | 4V < VVDD < 20V , Measure VBGATE – A ↓, when STAT↓ | 4 | 5 | 6 | V |
2.5V <VVDD < 4V , Measure VBGATE – A ↑, when STAT↑ | 2 | 2.7 | 3.4 | V | ||
VSTAT,LOWoff | STAT Output low voltage | Sinking 2 mA | 0.11 | 0.25 | V | |
ISTAT,LEAK | STAT Input leakage current | VSTAT = 0 V, 30 V | –1 | 0 | 1 | µA |
THERMAL SHUTDOWN (OTSD) | ||||||
TOTSD | Thermal shutdown threshold | Temperature rising | 140 | °C | ||
TOTSD,HYST | Hysteresis | 10 | °C |
PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT SUPPLY (VDD) | ||||||
DEGLUVLO | UVLO deglitch | Both rising and falling | 14 | µs | ||
HOT SWAP FET ENABLE (ENHS) | ||||||
DEGLENHS | Deglitch time | Both rising and falling | 2.2 | 3.8 | 5.5 | µs |
BLOCKING (ORING) FET ENABLE (ENOR) | ||||||
DEGLENOR | Deglitch time | Both rising and falling | 1.7 | 3.5 | 5 | µs |
OVER VOLTAGE (OV) | ||||||
DEGLOV | Deglitch time | Both rising and falling | 2.2 | 3.9 | 5.7 | µs |
HOT SWAP GATE DRIVER (HGATE) | ||||||
tHGATEdly | Turn on delay | CP ↑ to IHGATE sourcing | 1.9 | ms | ||
FAST TRIP (FSTP) | ||||||
tFastOffDly | Fast turn-off delay | V(FSTP – SENM) : –5mV to 5mV, CHGATE = 0 pF | 600 | ns | ||
V(FSTP – SENM) : -20mV to 20mV CHGATE = 0 pF | 300 | |||||
tFastOffDur | Strong pull down current duration | 53 | 63 | 73 | µs | |
INRUSH TIMER (TINR) | ||||||
NRETRY | Number of TINR cycles before retry | TPS24741 only | 64 | |||
RETRYDUTY | Retry duty cycle | TINR not connected to TFLT | 0.35% | |||
TINR connected to TFLT | 0.7% | |||||
BLOCKING/ORING GATE DRIVER (BGATE) | ||||||
tFastOffDur | Strong pull down current duration | 10 | 15 | 20 | µs | |
tFastOnDur | Strong pull up current duration | 10 | 20 | 30 | µs | |
POSITIVE INPUT OF REVERSE VOLTAGE COMPARATOR (RVSNP) | ||||||
tFastOffDly | Turn-off delay | V(RVSNP –RVSNM) = –5mV → 5mV, CBGATE = 0 pF |
340 | ns | ||
V(RVSNP –RVSNM) = –20mV → +20mV, CBGATE = 0 pF |
150 | |||||
FAULT INDICATOR (FLTb) | ||||||
tFLT_degl | HS / OR Fault Deglitch | Both HS and ORing faults | 2.2 | 3.9 | 5.3 | ms |
tFLT_CP_degl | CP fault deglitch | 26.5 | 32 | 37.2 | ms | |
HOT SWAP POWER GOOD OUTPUT (PGHS) | ||||||
tPGHSdegl | PGHS deglitch time | Rising | 0.7 | 1 | 1.3 | ms |
Falling | 7 | 8 | 9 | |||
STATUS INDICATOR (STAT) | ||||||
tSTATdegl | STAT Delay (deglitch) time | Rising or falling edge | 0.4 | 0.95 | 1.5 | ms |
Iq = IVDD + IA + IC + IOUTH |
IPGHS = 2mA |
VIMON during Power Limiting |
VHGATE - VOUTH = 2V |
VBGATE - VA = 4V | ||
Sustained Sink Current |
ISTAT = 2mA |
VHGATE - VOUTH = 10V |
VBGATE - VA = 10V | ||
Sustained Sink Current |
VHGATE-OUTH =4V |
TPS2474x is a Hot Swap and ORing controller with many programmable settings. In addition the ORing and Hot Swap blocks are set-up independently, which allows for the interchangeable order of Hot Swap and ORing. For the ORing controller the RVSNM and RVSNP serve as a way to program the reverse voltage threshold and sense the reverse voltage. The Hot Swap features a programmable current limit, power limit, and fast trip threshold. It also has dual timers: one for inrush and one during over current faults. Finally it features an analog current monitor that can be used to provide current information to a microcontroller.
The ORing function of the TPS2474x runs from an internal bus (VINT), which is derived from ORing A, C, and VDD. This ensures that the TPS2474x can stay powered and functions properly, even if the input or output are shorted to GND. The ORing function's UVLO is derived based on the VINT rail. This does mean that the part can draw up to 3 mA from the A or C pin. Hence it is recommended to keep traces to these pins fairly short and to avoid adding resistors in the path.
Both the Hot Swap section and the ORing section can be independently enabled with the ENHS and ENOR pins respectively. The part is enabled when the pin voltage exceeds 1.35V and is disabled when the pin voltage falls under 1.3V providing 50mV of hysteresis. A resistor divider can be connected to these pins to turn on the TSP2474x at a certain bus voltage. Both the ORing and the Hot Swap FETs will be turned off if the OV pin exceeds 1.35V.
The current limit and power limit of the TPS2474x are programmable to protect the load, power supply, and the Hot Swap MOSFET. During start-up the active control loop will regulate the gate to ensure that the current through the MOSFET and the power dissipation of the MOSFET is below their respective pre-programmed thresholds. The maximum current allowed through the MOSFET (ILIM) is determined with Equation 1. ILIM,CL is the programmed current limit, PLIM is the programmed power limit, and VDS is the drain to source voltage across the Hot Swap MOSFET.
This results in an IV curve shown in Figure 20. ILIM,PL denotes the maximum allowed MOSFET current (IDS) when the part is in power limit. As VDS increases, ILIM,PL decreases and ILIM,PL,MIN denotes the lowest ILIM,PL, which occurs at the largest VDS (VDS,MAX). The TPS2474x enforce this by regulating the voltage across RSNS (VSNS). VSNS,PL denotes VSNS when power limiting is active. Similarly to ILIM,PL, VSNS,PL decreases as VDS increases and VSNS,PL,MIN corresponds to the lowest VSNS,PL, which occurs at VDS,MAX. VSNS,CL is a current limiting sense voltage, which is programmable in the TPS2474x.
The current and power limit can be programmed using the equations below.
Note, that the error is largest at VSNS,PL,MIN due to offset of the internal amplifier. Also the operation at VDS,MAX is most critical because it corresponds to the short circuit condition and has the biggest impact on start time. Thus it is critical to consider VSNS,PL,MIN during design. Equation 5 shows the relationship of VSNS,PL,MIN as a function of PLIM, ILIM,CL, VSNS,CL, and VDS,MAX. Note that ILIM,CL and VDS,MAX are usually determined by the system requirements. The designer will have control over PLIM and VSNS,CL. In general, there will be a desire to reduce the power limit to allow for smaller MOSFETs and to reduce the VSNS,CL to improve efficiency (lower RSNS). However, this will also reduce VSNS,PL,MIN and the designer should ensure that it's above the miminum recommended value of 1.5mV.
After the TPS2474x has gone through start-up it will no longer actively control HGATE. Instead it will run the timer when the current is between the current limit and the fast trip threshold. Once the timer has expired the gate will be pulled down. If the current ever exceeds the fast trip threshold, HGATE will be pulled down immediately.
TPS2474x has two timer pins to allow the user to customize the protection. The TINR pin sources 10.25 µA when the device is in start-up mode and is actively regulating the gate to limit the MOSFET power or current. It sinks 2 µA otherwise. The TFLT pin sources 10.25 µA when the device is in regular operation and the FET current exceeds the current limit. It sinks 2 µA otherwise. If either of the timer pins exceeds 1.35, the TPS2474x times out. The TPS24740 and TPS24742 latches off. The TPS24741 goes through 64 cycles of TINR and attempts to start-up again.
Since the TINR usually runs when the MOSFET is being stressed, TINR should be sized to maintain the FET within its SOA. In general TFLT runs when the load is drawing more current than expected, which can stress the load and the power supply. Thus TFLT should be programmed to have the right protection settings for the power supply and the load. In some systems the load is allowed to draw current above the current limit for a prolonged time. In that case a large TFLT is required, but a short TINR may still be desired to minimize the worst case FET stress. In other applications a long TINR may be required to due to large downstream capacitances, but drawing excessive current from the power supply for more than 5ms is not desired. In that case a short TFLT and a long TINR should be used. Finally, many applications can use the same TINR and TFLT setting, in which case the pins can be tied together and a single capacitor can be used. The two different options are shown in Figure 21.
If two separate timer capacitors are used their values can be computed with Equation 6 and Equation 7:
If a single capacitor is used CTMR can be computed with Equation 8.
During start-up the TPS2474x regulates the HGATE to keep the FET power dissipation within PLIM. This is accomplished by an amplifier that monitors the IMON voltage and an internal reference voltage. The TPS24740 will source current into HGATE if VIMON is lower than the reference voltage and will sink current into HGATE if VIMON is above the reference voltage. In steady state, the VIMON will be regulated to the VIMON,PL point, where IHGATE equals zero. Note that VIMON,PL is determined by RPLIM and the VSENM – VOUTH.
The same amplifier feeds into the inrush timer circuitry to run the timer when the part is in power limit. The VIMON threshold at which the timer starts to source current is denoted as VIMON, TINR. Note that VIMON,TINR is lower than VIMON,PL to account for tolerances and ensure that the timer is always active when the device is in power limit. The difference between the two thresholds is defined as ΔVIMON, TINR. A typical curve of the IHGATE and ITINR is available in the typical characteristics section.
It is critical to consider ΔVIMON, TINR and Figure 22 if a soft start circuit is used. Typically, the soft start is implemented by limiting the gate dv/dt with a capacitor, which in turn limits the inrush current to the output capacitor. Often times, the inrush current is kept below ILIM,PL to keep the timer from running. Note that the ILIM,PL is based on the VIMON,PL threshold and thus TINR can be activated even if the inrush current is below ILIM,PL. To prevent the timer from running unintentionally, it's important that the minimum power limit (typical PLIM - tolerance) is above PLIM,MIN,SS, which can be computed as shown in Equation 9 below. As an example, consider the usage case where the maximum inrush current (IINR,MAX) is 2A, the maximum input voltage (VIN,MAX) is 13V and RSET, RIMON, and RSNS are 100Ω, 2.7kΩ, and 1mΩ respectively. For that case the power limit should be set to at least 58.3 W + PLIM tolerance to ensure that the inrush timer does not run.
The TPS24740, TPS24741, and TPS24742 have difference responses to a fast trip event to accommodate different design requirements. When the current exceeds the fast trip threshold, the gate is quickly pulled down to minimize damage that can be caused due to a short circuit. Figure 23 shows the response of the variate devices options to a Hotshort on the output. The TPS24740 (latch) attempts to re-start once after the hot-short is observed and then stay off. The TPS24741 continuously retries with a duty cycle of ~0.5% (0.7% if TFLT and TINR are connected, 0.35% if TFLT and TINR are not connected); and, the TPS24742 shuts off and never retries again. In general the TPS24742 (Fast/immediate Latch Off) places the least amount of stress on the MOSFET, but is the least likely to recover from a nuisance trip.
The TPS2474x has a programmable reverse voltage threshold. An internal comparator detects a reverse current condition when RVSNP is above RVSNM. This signal is used to shut off the ORing MOSFET. RRV along with a 99µA current source pre-bias RVSNP to below the real source voltage of the MOSFET and effectively set the reverse voltage threshold. CRV along with RRV filters transients across the drain to source of the ORing FET.
Note that the RVSNM and RVSNP can be connected at various places. One option is to connect it across the drain to source of the ORing FET (Figure 24), which would result in a reverse current threshold of VRV/RDSON. Another option is to connect across the RSNS as shown in Figure 25. This could be useful if a precise threshold is desired and RSNS is larger than the RDSON of the ORing FET.
The TPS2474x also features two analog current monitoring outputs: IMON and IMONBUF. Each has their own advantages and disadvantages. The IMON is more accurate, because it doesn’t have the error added from the second stage. However it is a high impedance output and leakage current on that node would result in monitoring error. In addition it can only support 30pF of capacitance and its full scale range is 675mV (this is where current limit kicks in). The IMONBUF takes the IMON signal and buffers it 3x. This introduces more error, but the output is low impedance, has a larger full scale range, and can drive up to 100pF of capacitance.
The TPS2474x has a power good flag, which should be used to turn on downstream DC/DC converters. This reduces the stress on the Hot Swap MOSFET during start-up. The PGHS pin of the TPS2474x is asserted (with 1 ms deglitch) when both:
PGHS is de-asserted (with 8 ms deglitch) when either:
The TPS2474x, features a STAT flag that indicates whether the BGATE (ORing FET driver) is ON or OFF. In general it is good practice to have the ORing FETs ON before drawing any significant load to prevent the ORing FET from overheating.
TPS 2474x will assert a fault by pulling down on the FLTb pin if any of the following occur:
Figure 27 shows the logic for the fault conditions.
The Hot Swap and ORing section of the TPS2474x are for the most part independent. The only exception is that the Hot Swap is gated by the charge pump being up. This ensures that the ORing FET is ON before the Hot Swap turns on to avoid a possible glitch from a fast ORing turn on.
Figure 28 shows the state machine for the ORing portion of the controller. It has three modes listed below:
The state machine for the Hot Swap section is shown in Figure 29. After a POR / UVLO event the Hot Swap waits 1.9ms after the charge pump is up before starting up. Once operational the Hot Swap has the following functional modes: