The TPS254900-Q1 device is a USB charging-port controller and power switch with short-to-battery protection. This feature provides protection on OUT, DM_IN and DP_IN. These three pins withstand voltage up to 18 V. The internal MOSFET turns off quickly when the short-to-battery condition occurs. Rapid turnoff is very important to protect the upstream dc-dc converter, processor, or hub data lines.
The TPS254900-Q1 45-mΩ power switch has two selectable, adjustable current limits that support port power management by changing to a lower current limit when adjacent ports are experiencing heavy loads. This is important in systems with multiple ports and upstream power supplies with limited capacity.
The TPS254900-Q1 has a current-sense output that is able to control an upstream supply, which allows it to maintain 5 V at the USB port even with heavy charging currents. This feature is important in systems with long USB cables where significant voltage drops can occur with fast-charging portable devices.
A current monitor allows a system to monitor the load current in real time by monitoring the IMON voltage. The current monitor is very useful and can be used for dynamic port-power management.
The TPS254900-Q1 device also provides ESD protection capability per IEC 61000-4-2, level 4 on DP_IN and DM_IN.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS254900-Q1 | WQFN (20) | 3.00 mm × 4.00 mm |
Changes from * Revision (September 2016) to A Revision
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
BIAS | 12 | PWR | Used for IEC protection. Typically, connect a 2.2-µF capacitor and a transient-voltage suppressor (TVS) to ground and 5.1 kΩ to OUT. |
CS | 6 | O | Linear cable compensation current. Connect to divider resistor of front-end dc-dc converter. |
CTL1 | 8 | I | Logic-level control input for controlling the charging mode and the signal switches; see the Device Truth Table (TT). |
CTL2 | 9 | I | Logic-level control input for controlling the charging mode and the signal switches; see the Device Truth Table (TT). |
DM_IN | 14 | I/O | D– data line to downstream connector |
DM_OUT | 4 | I/O | D– data line to upstream USB host controller |
DP_IN | 13 | I/O | D+ data line to downstream connector |
DP_OUT | 5 | I/O | D+ data line to upstream USB host controller |
EN | 7 | I | Logic-level control input for turning the power and signal switches on or off. When EN is low, the device is disabled, and the signal and power switches are OFF. |
FAULT | 18 | O | Active-low, open-drain output, asserted during overtemperature, overcurrent, and overvoltage conditions. |
GND | 11 | — | Ground connection; should be connected externally to the thermal pad. |
ILIM_HI | 20 | I | External resistor used to set the high current-limit threshold. |
ILIM_LO | 19 | I | External resistor used to set the low current-limit threshold and the load-detection current threshold. |
IMON | 1 | O | This pin sources a scaled-down ratio of current through the internal FET. A resistor from this pin to GND converts current to proportional voltage; used as an analog current monitor. |
IN | 2,3 | PWR | Input supply voltage; connect a 0.1-µF or greater ceramic capacitor from IN to GND as close to the IC as possible. |
OUT | 15,16 | PWR | Power-switch output |
OVP_SEL | 10 | I | Logic-level control input for choosing the OUT overvoltage threshold. When OVP_SEL is low, V(OV_OUT_LOW) is active. When OVP_SEL is high, V(OV_OUT_HIGH) is active. |
STATUS | 17 | O | Active-low open-drain output, asserted in load-detect conditions |
Thermal pad | — | — | Thermal pad on the bottom of the package |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Voltage range | CS, CTL1, CTL2, EN, FAULT, ILIM_HI, ILIM_LO, IN, IMON, OVP_SEL, STATUS | –0.3 | 7 | V | |
DM_OUT, DP_OUT | –0.3 | 5.7 | |||
BIAS, DM_IN, DP_IN, OUT | –0.3 | 18 | |||
Continuous current | DM_IN to DM_OUT or DP_IN to DP_OUT | –100 | 100 | mA | |
OUT | Internally limited | ||||
ISRC | Continuous output source current | ILIM_HI, ILIM_LO, IMON | Internally limited | A | |
ISNK | Continuous output sink current | FAULT, STATUS | 25 | mA | |
CS | Internally limited | A | |||
TJ | Operating junction temperature | –40 | Internally limited | °C | |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2 000(2) | V | |
Charged-device model (CDM), per AEC Q100-011 | ±750(3) | ||||
IEC 61000-4-2 contact discharge, DP_IN and DM_IN(4) | ±8 000 | ||||
IEC 61000-4-2 air discharge, DP_IN and DM_IN(4) | ±15 000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
V(IN) | Supply voltage | IN | 4.5 | 6.5 | V | |
Input voltage | CTL1, CTL2, EN, OVP_SEL | 0 | 6.5 | V | ||
DM_IN, DM_OUT, DP_IN, DP_OUT | 0 | 3.6 | V | |||
I(OUT) | Output continuous current | OUT (–40°C ≤ TA ≤ 85°C) | 3 | A | ||
DM_IN to DM_OUT or DP_IN to DP_OUT | –30 | 30 | mA | |||
Continuous output sink current | FAULT, STATUS | 10 | mA | |||
R(ILIM_xx) | Current-limit-set resistors | 14.3 | 1000 | kΩ | ||
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS254900-Q1 | UNIT | |
---|---|---|---|
RVC (WQFN) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 37.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 39.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 11.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 11.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
OUT – POWER SWITCH | ||||||
rDS(on) | On-resistance(1) | TJ = 25°C | 45 | 55 | mΩ | |
–40°C ≤ TJ ≤ 85°C | 45 | 69 | ||||
–40°C ≤TJ ≤ 125°C | 45 | 77 | ||||
Ilkg | Reverse leakage current | VOUT = 6.5 V, VIN = VEN = 0 V, –40°C ≤ TJ ≤ 85°C, measure I(IN) | 0.01 | 2 | µA | |
OUT – DISCHARGE | ||||||
R(DCHG) | Discharge resistance (mode change) | 400 | 500 | 630 | Ω | |
CTL1, CTL2, EN, OVP_SEL INPUTS | ||||||
Input pin rising logic threshold voltage | 1 | 1.35 | 2 | V | ||
Input pin falling logic threshold voltage | 0.85 | 1.15 | 1.65 | V | ||
Hysteresis(2) | 200 | mV | ||||
Input current | Pin voltage = 0 V or 6.5 V | –1 | 1 | µA | ||
CURRENT LIMIT | ||||||
IOS | OUT short-circuit current limit | R(ILIM_LO) = 210 kΩ | 190 | 240 | 290 | mA |
R(ILIM_LO) = 80.6 kΩ | 555 | 620 | 680 | |||
R(ILIM_LO) = 21.5 kΩ | 2145 | 2300 | 2460 | |||
R(ILIM_LO) = 19.1 kΩ | 2420 | 2590 | 2760 | |||
R(ILIM_HI) = 18.2 kΩ | 2545 | 2720 | 2895 | |||
R(ILIM_HI) = 14.3 kΩ | 3240 | 3455 | 3670 | |||
R(ILIM_HI) shorted to GND | 5000 | 6500 | 8000 | |||
SUPPLY CURRENT | ||||||
I(IN_OFF) | Disabled IN supply current | V(EN) = 0 V, V(OUT) = 0 V, –40°C ≤ TJ ≤ 85°C, no 5.1-kΩ resistor (open) between BIAS and OUT | 0.1 | 5 | µA | |
I(IN_ON) | Enabled IN supply current | SDP mode (CTL1, CTL2 = 0, 1) | 170 | 250 | µA | |
CDP mode (CTL1, CTL2 = 1, 1) | 200 | 280 | ||||
Client mode (CTL1, CTL2 = 0, 0) | 120 | 210 | ||||
UNDERVOLTAGE LOCKOUT, IN | ||||||
V(UVLO) | UVLO threshold voltage | IN rising | 3.9 | 4.15 | 4.3 | V |
Hysteresis(3) | TJ = 25°C | 100 | mV | |||
FAULT | ||||||
Output low voltage | I(FAULT) = 1 mA | 100 | mV | |||
Off-state leakage | V(FAULT) = 6.5 V | 2 | µA | |||
STATUS | ||||||
Output low voltage | I(STATUS) = 1 mA | 100 | mV | |||
Off-state leakage | V(STATUS) = 6.5 V | 2 | µA | |||
THERMAL SHUTDOWN | ||||||
T(OTSD2) | Thermal shutdown threshold | 155 | °C | |||
T(OTSD1) | Thermal shutdown threshold in current-limit | 135 | °C | |||
Hysteresis(3) | 20 | °C | ||||
LOAD DETECT (VCTL1 = VCTL2 = VIN) | ||||||
I(LD) | IOUT load detection threshold | R(ILIM_LO) = 80.6 kΩ, rising load current | 585 | 650 | 715 | mA |
Hysteresis(3) | 50 | mA | ||||
DM_IN AND DP_IN OVERVOLTAGE PROTECTION | ||||||
V(OV_Data) | Protection trip threshold | DP_IN and DM_IN rising | 3.7 | 3.9 | 4.15 | V |
Hysteresis(3) | 100 | mV | ||||
R(DCHG_Data) | Discharge resistor after OVP(2) | DP_IN = DM_IN = 18 V, IN = 5 V or 0 V | 200 | kΩ | ||
DP_IN = DM_IN = 5 V, IN = 5 V | 370 | |||||
DP_IN = DM_IN = 5 V, IN = 0 | 390 | |||||
OUT OVERVOLTAGE PROTECTION | ||||||
V(OV_OUT_LOW) | Protection trip threshold | OUT rising | 5.65 | 6 | 6.35 | V |
Hysteresis(3) | 90 | mV | ||||
V(OV_OUT_HIGH) | Protection trip threshold | OUT rising | 6.6 | 6.95 | 7.3 | V |
Hysteresis(3) | 130 | mV | ||||
R(DCHG_OUT) | Discharge resistor | OUT = 18 V, IN = 5 V | 55 | 85 | kΩ | |
OUT = 18 V, IN = 0 | 80 | 120 | ||||
CABLE COMPENSATION | ||||||
I(CS) | Sink current | Load = 3 A, 2.5 V ≤ V(CS) ≤ 6.5 V | 234 | 246 | 258 | µA |
Load = 2.4 A, 2.5 V ≤ V(CS) ≤ 6.5 V | 187 | 197 | 207 | |||
Load = 2.1 A, 2.5 V ≤ V(CS) ≤ 6.5 V | 163 | 172 | 181 | |||
Load = 1 A, 2.5 V ≤ V(CS) ≤ 6.5 V | 77 | 82 | 87 | |||
CURRENT MONITOR OUTPUT (IMON) | ||||||
I(IMON) | Source current | Load = 3 A, 0 ≤ V(IMON) ≤ 2.5 V | 287 | 312 | 337 | µA |
Load = 2.4 A, 0 ≤ V(IMON) ≤ 2.5 V | 230 | 250 | 270 | |||
Load = 2.1 A, 0 ≤ V(IMON) ≤ 2.5 V | 201 | 218 | 235 | |||
Load = 1 A, 0 ≤ V(IMON) ≤ 2.5 V | 94 | 104 | 114 | |||
Load = 0.5 A, 0 ≤ V(IMON) ≤ 2.5 V | 44 | 52 | 60 | |||
HIGH-BANDWIDTH ANALOG SWITCH | ||||||
R(HS_ON) | DP and DM switch on-resistance | V(DP_OUT) = V(DM_OUT) = 0 V, I(DP_IN) = I(DM_IN) = 30 mA | 3.2 | 6.5 | Ω | |
V(DP_OUT) = V(DM_OUT) = 2.4 V, I(DP_IN) = I(DM_IN) = –15 mA | 3.8 | 7.6 | ||||
|ΔR(HS_ON)| | Switch resistance mismatch between DP and DM channels | V(DP_OUT) = V(DM_OUT) = 0 V, I(DP_IN) = I(DM_IN) = 30 mA | 0.05 | 0.15 | Ω | |
V(DP_OUT) = V(DM_OUT) = 2.4 V, I(DP_IN) = I(DM_IN) = –15 mA | 0.05 | 0.15 | ||||
C(IO_OFF) | DP and DM switch off-state capacitance(4) | VEN = 0 V, V(DP_IN) = V(DM_IN) = 0.3 V, Vac = 0.03 VPP , f = 1 MHz | 8.8 | pF | ||
C(IO_ON) | DP and DM switch on-state capacitance(4) | V(DP_IN) = V(DM_IN) = 0.3 V, Vac = 0.03 VPP, f = 1 MHz | 10.9 | pF | ||
Off-state isolation(3) | V(EN) = 0 V, f = 250 MHz | 8 | dB | |||
On-state cross-channel isolation(4) | f = 250 MHz | 30 | dB | |||
Ilkg(OFF) | Off-state leakage current | VEN = 0 V, V(DP_IN) = V (DM_IN) = 3.6 V, V(DP_OUT) = V(DM_OUT) = 0 V, measure I(DP_OUT) and I(DM_OUT) | 0.1 | 1.5 | µA | |
BW | Bandwidth (–3 dB)(4) | R(L) = 50 Ω | 940 | MHz | ||
CHARGING DOWNSTREAM PORT DETECT | ||||||
V(DM_SRC) | DM_IN CDP output voltage | V(DP_IN) = 0.6 V, –250 µA < I(DM_IN) < 0 µA | 0.5 | 0.6 | 0.7 | V |
V(DAT_REF) | DP_IN rising lower window threshold for V(DM_SRC) activation | 0.36 | 0.4 | V | ||
Hysteresis(4) | 50 | mV | ||||
V(LGC_SRC) | DP_IN rising upper window threshold for VDM_SRC de-activation | 0.8 | 0.88 | V | ||
V(LGC_SRC_HYS) | Hysteresis(4) | 100 | mV | |||
I(DP_SINK) | DP_IN sink current | V(DP_IN) = 0.6 V | 40 | 75 | 100 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tr | OUT voltage rise time | V(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω | 1.05 | 1.75 | 3.1 | ms |
tf | OUT voltage fall time | 0.27 | 0.47 | 0.82 | ms | |
ton | OUT voltage turnon time | V(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω | 7.5 | 11 | ms | |
toff | OUT voltage turnoff time | 2.7 | 5 | ms | ||
t(DCHG_S) | Discharge hold time (mode change) | Time V(OUT) < 0.7 V | 1.1 | 2 | 2.9 | s |
t(IOS) | OUT short-circuit response time(1) | V(IN) = 5 V, R(SHORT) = 50 mΩ | 2 | µs | ||
t(OC_OUT_FAULT) | OUT FAULT deglitch time | Bidirectional deglitch applicable to current-limit condition only (no deglitch assertion for OTSD) | 5.5 | 8.5 | 11.5 | ms |
tpd | Analog switch propagation delay (1) | V(IN) = 5 V | 0.14 | ns | ||
t(SK) | Analog switch skew between opposite transitions of the same port (tPHL – tPLH) (1) | V(IN) = 5 V | 0.02 | ns | ||
t(LD_SET) | Load-detect set time | V(IN) = 5 V | 120 | 210 | 280 | ms |
t(LD_RESET) | Load-detect reset time | V(IN) = 5 V | 1.8 | 3 | 4.2 | s |
t(OV_Data) | DP_IN and DM_IN overvoltage protection response time | 5 | µs | |||
t(OV_OUT) | OUT overvoltage protection response time | 0.3 | µs | |||
t(OV_D_FAULT) | DP_IN and DM_IN FAULT-asserted degltich time | 11 | 16 | 23 | ms | |
OUT FAULT-asserted degltich time | 11 | 16 | 23 | ms |
V(IN) = 5 V |
V(OUT) = 5 V | Measure I(OUT) |
A |
V(IN) = 5 V |
CTL1 = 1 | CTL2 = 1 |
V(IN) = 5 V | R(ILIM_LO) = 80.6 kΩ |
V(IN) = 5 V |
VIN = 6.5 V |
VIN = 4.5 V |
A |
V(IN) = 5 V |
CTL1 = 1 | CTL2 = 1 |
V(IN) = 5 V |
V(IN) = 5 V | V(CS) = 25 V |
VIN = 5 V | V(IMON) = 25 V |
Measured on EVM with 10-cm cable |
R(LOAD) = 5 Ω | C(LOAD) = 10 µF | t = 2 ms/div |
Measured on EVM with 10-cm cable |
R(LOAD) = 5 Ω | C(LOAD) = 10 µF | t = 1 ms/div |
R(ILIM_LO) = 80.6 kΩ | t = 4 ms/div |
R(ILIM_LO) = 80.6 kΩ | t = 2 ms/div |
R(ILIM_HI) = 19.1 kΩ | R(short) = 50 mΩ | t = 2 ms/div |
R(ILIM_LO) = 80.6 kΩ | t = 1 s/div |
t = 100 ms/div |
R(BIAS) = 5.1 kΩ | t = 100 ms/div |
R(BIAS) = 5.1 kΩ | t = 200 ms/div |
R(ILIM_HI) = 19.1 kΩ | t = 4 ms/div |
R(ILIM_HI) = 19.1 kΩ | t = 4 ms/div |
R(ILIM_LO) = 80.6 kΩ | t = 100 ms/div |
t = 4 ms/div |
t = 4 ms/div |
R(BIAS) = 5.1 kΩ | t = 4 ms/div |
The TPS254900-Q1 device is a USB charging controller and power switch which integrates D+ and D– short-to-battery protection, cable compensation, current monitor (IMON), and IEC ESD protection suitable for automotive USB charging and USB port protection applications.
The integrated power distribution switch uses N-channel MOSFETs suitable for applications where short circuits or heavy capacitive loads will be encountered. The device allows the user to adjust the current-limit thresholds using external resistors. The device enters constant-current mode when the load exceeds the current-limit threshold.
The TPS254900-Q1 device provides VBUS, D+, and D– short-to-battery protection. This protects the upstream voltage regulator, automotive processor, and hub when these pins are exposed to fault conditions.
The device also integrates CDP mode, defined in the BC1.2 specification, to enable up to 1.5-A fast charging of most portable devices during data communication.
The TPS254900-Q1 device integrates a cable compensation (CS) feature to compensate for long-cable voltage drop. This keeps the remote USB port output voltage constant to enhance the user experience under high-current charging conditions.
The TPS254900-Q1 device provides a current-monitor function (IMON) by connecting a resistor from the IMON pin to GND to provide a positive voltage linearly with load current. This can be used for system power or dynamic power management.
Additionally, the device provides ESD protection up to ±8 kV (contact discharge) and ±15 kV (air discharge) per IEC 61000-4-2 on DP_IN and DM_IN.
The device features an active-low, open-drain fault output. FAULT goes low when there is a fault condition. Fault detection includes overtemperature, overcurrent, or overvoltage on VBUS, DP_IN and DM_IN. Connect a 10-kΩ pullup resistor from FAULT to IN.
Table 1 summarizes the conditions that generate a fault and actions taken by the device.
EVENT | CONDITION | ACTION |
---|---|---|
Overvoltage on the data lines | V(DP_IN) or V(DM_IN) > 3.9 V | The device immediately shuts off the USB data switches and the internal power switch. The fault indicator asserts with a 16-ms deglitch, and deasserts without deglitch. |
Overvoltage on V(OUT) | V(OUT) > 6 V or 6.95 V | The device immediately shuts off the internal power switch and the USB data switches. The fault indicator asserts with a 16-ms deglitch and deasserts without deglitch. |
Overcurrent on V(OUT) | I(OUT) > I(OS) | The device regulates switch current at I(OS) until thermal cycling occurs. The fault indicator asserts and deasserts with an 8-ms deglitch (the device does not assert FAULT on overcurrent in SDP1 mode). |
Overtemperature | TJ > OTSD2 in non-current-limited or TJ > OTSD1 in current-limited mode. | The device immediately shuts off the internal power switch and the USB data switches. The fault indicator asserts immediately when the junction temperature exceeds OTSD2 or OTSD1 while in a current-limiting condition. The device has a thermal hysteresis of 20°C. |
When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered to the load. In the vehicle from the voltage regulator 5-V output to the VPD_IN (input voltage of portable device), the total resistance of power switch rDS(on) and cable resistance causes an IR drop at the PD input. So the charging current of most portable devices is less than their expected maximum charging current.
TPS254900-Q1 device detects the load current and applies a proportional sink current that can be used to adjust the output voltage of the upstream regulator to compensate for the IR drop in the charging path. The gain G(CS) of the sink current proportional to load current is 82 µA/A.
To start the procedure, the total resistance, including the power switch rDS(on) and wire resistance R(WIRE), must be known.
D+ and D– protection consists of ESD and OVP (overvoltage protection). The DP_IN and DM_IN pins provide ESD protection up to ±15 kV (air discharge) and ±8 kV (contact discharge) per IEC 61000-4-2 (see the ESD Ratings section for test conditions).
The ESD stress seen at DP_IN and DM_IN is impacted by many external factors, like the parasitic resistance and inductance between ESD test points and the DP_IN and DM_IN pins. For air discharge, the temperature and humidity of the environment can cause some difference, so the IEC performance should always be verified in the end-application circuit.
The IEC ESD performance of the TPS254900-Q1 device depends on the capacitance connected from BIAS to GND. A 2.2-µF capacitor placed close to the BIAS pin is recommended. Connect the BIAS pin to OUT using a 5.1-kΩ resistor as a discharge path for the ESD stress.
OVP protection is provided for short-to-VBUS or short-to-battery conditions in the vehicle harness, preventing damage to the upstream USB transceiver or hub. When the voltage on DP_IN or DM_IN exceeds 3.9 V (typical), the TPS254900-Q1 device quickly responds to block the high-voltage reverse connection to DP_OUT and DM_OUT. Overcurrent short-to-GND protection for D+ and D– is provided by the upstream USB transceiver.
The TPS254900-Q1 OUT pin can withstand up to 18 V. The internal MOSFET turns off quickly when a short-to-battery condition occurs.
The TPS254900-Q1 device has two OVP thresholds; one is 6 V (typical) and the other is 6.95 V (typical). Set the OVP threshold using the external OVP_SEL pin.
To allow a charging port to renegotiate current with a portable device, the TPS254900-Q1 device uses the OUT discharge function. During mode change, the TPS254900-Q1 device turns off the power switch while discharging OUT with a 500-Ω resistance, then turning back on the power switches to reassert the OUT voltage.
When an OVP condition occurs on DP_IN or DM_IN, the TPS254900-Q1 device enables an internal 200-kΩ discharge resistance from DP_IN to ground and from DM_IN to ground. The analog switches are also turned off. The TPS254900-Q1 device automatically disables the discharge paths and turns on the analog switches once the OVP condition is removed.
When an OVP condition occurs on OUT, the TPS254900-Q1 device turns on an internal discharge path (see Table 2 for the discharge resistance). The TPS254900-Q1 device automatically turns off the discharge path and turns on the power switch once the OVP condition is removed.
PPM is the intelligent and dynamic allocation of power. PPM is for systems that have multiple charging ports but cannot power them all simultaneously.
The benefits of PPM include the following:
All ports are allowed to broadcast high-current charging. The current limit is based on ILIM_HI. The system monitors the STATUS pin to see when high-current loads are present. Once the allowed number of ports asserts STATUS, the remaining ports are toggled to a non-charging port. The current limit of the non-charging port is based on the ILIM_LO setting. The non-charging ports are automatically toggled back to charging ports when a charging port deasserts STATUS.
STATUS asserts in a charging port when the load current is above ILIM_LO + 30 mA for 210 ms (typical). STATUS deasserts in a charging port when the load current is below ILIM_LO – 20 mA for 3 seconds (typical).
Figure 39 shows the implementation of the two charging ports with data communication, each with a TPS254900-Q1 device and configured in CDP mode. In this example, the 5-V power supply for the two charging ports is rated at less than 3.5 A. Both TPS254900-Q1 devices have R(ILIM) chosen to correspond to the low (1-A) and high (2.4-A) current-limit setting for the port. In this implementation, the system can support only one of the two ports at 2.4-A charging current, whereas the other port is set to the SDP1 mode and IOS corresponds to 1 A.
When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output is shorted before the device is enabled or before the application of V(IN). The TPS254900-Q1 device senses the short and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs, high currents flow for 1 to 2 μs (typical) before the current-limit circuit reacts. The device operates in constant-current mode after the current-limit circuit has responded. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. The device remains off until the junction temperature cools approximately 20°C and then restarts. The device continues to cycle on and off until the overcurrent condition is removed.
The undervoltage-lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turnon threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from large current surges.
Two independent thermal-sensing circuits protect the TPS254900-Q1 device if the temperature exceeds recommended operating conditions. These circuits monitor the operating temperature of the power-distribution switch and disable operation. The power dissipation in the package is proportional to the voltage drop across the power switch, so the junction temperature rises during an overcurrent condition. The first thermal sensor turns off the power switch when the die temperature exceeds 135ºC and the device is in current limit. The second thermal sensor turns off the power switch when the die temperature exceeds 155ºC regardless of whether the power switch is in current limit. Hysteresis is built into both thermal sensors, and the switch turns on after the device has cooled by approximately 20°C. The switch continues to cycle off and then on until the fault is removed. The open-drain false-reporting output, FAULT, is asserted (low) during an overtemperature shutdown condition.
The TPS254900-Q1 has two independent current-limit settings that are each adjusted externally with a resistor. The ILIM_HI setting is adjusted with R(ILIM_HI) connected between ILIM_HI and GND. The ILIM_LO setting is adjusted with R(ILIM_LO) connected between ILIM_LO and GND. Consult the device truth table (Table 3) to see when each current limit is used. Both settings have the same relation between the current limit and the adjusting resistor.
The following equation calculates the value of resistor for adjusting the typical current limit:
Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance limits, both the tolerance of the TPS254900-Q1 current limit and the tolerance of the external adjusting resistor must be taken into account. The following equations approximate the TPS254900-Q1 minimum and maximum current limits to within a few milliamperes and are appropriate for design purposes. The equations do not constitute part of TI’s published device specifications for purposes of TI’s product warranty. These equations assume an ideal—no variation—external adjusting resistor. To take resistor tolerance into account, first determine the minimum and maximum resistor values based on its tolerance specifications and use these values in the equations. Because of the inverse relation between the current limit and the adjusting resistor, use the maximum resistor value in the IOS(min) equation and the minimum resistor value in the IOS(max) equation.
The routing of the traces to the R(ILIM_xx) resistors should have a sufficiently low resistance so as not to affect the current-limit accuracy. The ground connection for the R(ILIM_xx) resistors is also very important. The resistors must reference back to the TPS254900-Q1 GND pin. Follow normal board layout practices to ensure that current flow from other parts of the board does not impact the ground potential between the resistors and the TPS254900-Q1 GND pin.
The device truth table (Table 3) lists all valid combinations for both control pins (CTL1 and CTL2), and the corresponding charging mode. The TPS254900-Q1 device monitors the CTL inputs and transitions to the charging mode to which it is commanded.
CTL1 | CTL2 | CURRENT LIMIT SELECTED | MODE | STATUS for Load Detect | CS FOR CABLE COMPENSATION | IMON FOR CURRENT MONITOR | FAULT REPORT | NOTES |
---|---|---|---|---|---|---|---|---|
0 | 0 | N/A | Client mode(1) | OFF | OFF | OFF | OFF | Power switch is disabled, only analog switch is on. |
0 | 1 | ILIM_LO | SDP | OFF | ON | ON | ON | Standard SDP |
1 | 0 | ILIM_LO | SDP1(2) | OFF | ON | ON | ON(3) | No OUT discharge between CDP and SDP1 for PPM |
1 | 1 | ILIM_HI | CDP(2) | ON | ON | ON | ON |
The BC1.2 specification includes three different port types:
BC1.2 defines a charging port as a downstream-facing USB port that provides power for charging portable equipment. Under this definition, CDP and DCP are defined as charging ports.
Table 4 lists the difference between these port types.
PORT TYPE | SUPPORTS USB2.0 COMMUNICATION | MAXIMUM ALLOWABLE CURRENT DRAWN BY PORTABLE EQUIPMENT (A) |
---|---|---|
SDP (USB 2.0) | YES | 0.5 |
SDP (USB 3.0) | YES | 0.9 |
CDP | YES | 1.5 |
DCP | NO | 1.5 |
An SDP is a traditional USB port that follows the USB 2.0 or USB 3.0 protocol. An SDP supplies a minimum of 500 mA per port for USB 2.0 and 900 mA per port for USB 3.0. USB 2.0 and USB 3.0 communication is supported, and the host controller must be active to allow charging.
A CDP is a USB port that follows the USB BC1.2 specification and supplies a minimum of 1.5 A per port. A CDP provides power and meets the USB 2.0 requirements for device enumeration. USB 2.0 communication is supported, and the host controller must be active to allow charging. The difference between CDP and SDP is the host-charge handshaking logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and allows for additional current draw by the client device.
The CDP handshaking process occurs in two steps. During the first step, the portable equipment outputs a nominal 0.6-V output on the D+ line and reads the voltage input on the D– line. The portable device detects the connection to an SDP if the voltage is less than the nominal data-detect voltage of 0.3 V. The portable device detects the connection to a CDP if the D– voltage is greater than the nominal data-detect voltage of 0.3 V and optionally less than 0.8 V.
The second step is necessary for portable equipment to determine whether the equipment is connected to a CDP or a DCP. The portable device outputs a nominal 0.6-V output on the D– line and reads the voltage input on the D+ line. The portable device concludes the equipment is connected to a CDP if the data line being read remains less than the nominal data detects voltage of 0.3 V. The portable device concludes it is connected to a DCP if the data line being read is greater than the nominal data-detect voltage of 0.3 V.
The TPS254900-Q1 integrates CDP detection protocol, used at a downstream port as the CDP controller to support CDP portable-device fast charge up to 1.5 A.
The TPS254900-Q1 device integrates client mode as shown in Figure 42. The internal power switch is OFF to block current flow from OUT to IN, and the signal switches are ON. This mode can be used for software upgrades from the USB port.
Passing the IEC 61000-4-2 test for DP_IN and DM_IN requires connecting a discharge resistor to OUT during USB 2.0 high-speed enumeration. In client mode, because the power switch is OFF, OUT must be 5 V so that the device can work normally (usually powered by an external downstream USB port). If the OUT voltage is low, the communication may not work properly.
The D+ and D– data lines pass through the device to enable monitoring and handshaking while supporting the charging operation. A wide-bandwidth signal switch allows data to pass through the device without corrupting signal integrity. The data-line switches are turned on in any of the CDP, SDP or client operating modes. The EN input must be at logic high for the data-line switches to be enabled.
NOTE
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS254900-Q1 device is a USB charging-port controller and power switch with cable compensation and short-to-battery protection for VBUS, D+, and D–. The device is typically used for automotive USB port protection and as a USB charging controller. The following design procedure can be used to select components for the TPS254900-Q1. This section presents a simplified discussion of how to choose external components for VBUS, D+, and D– short-to-battery protection. For cable-compensation design information, see the data sheet (SLUSCE3) for the TPS2549-Q1 device, which has features and design considerations very similar to those of the TPS254900-Q1 device.
For an automotive USB charging port, the VBUS, D+, and D– pins are exposed and require a protection device. The protection required includes VBUS overcurrent, D+ and D– ESD protection, and short-to-battery protection. This charging-port device protects the upstream dc-dc converter (bus line) and automotive SOC or hub chips (D+ and D– data lines). An application schematic of this circuit with short-to-battery protection is shown in Figure 43.
For this design example, use the following as the input parameters.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Battery voltage, V(BAT) | 18 V |
Short-circuit cable | 0.5 m |
To begin the design process, the designer must know the following:
Consider the following application situations when choosing the input capacitors.
For all applications, TI recommends a 0.1-µF or greater ceramic bypass capacitor between IN and GND, placed as close as possible to the device for local noise decoupling.
During output short or hot plug-in of a capacitive load, high current flows through the TPS254900-Q1 device back to the upstream dc-dc converter until the TPS254900-Q1 device responds (after t(IOS)). During this response time, the TPS254900-Q1 input capacitance and the dc-dc converter output capacitance source current to keep VIN above the UVLO of the TPS254900-Q1 device and any shared circuits. Size the input capacitance for the expected transient conditions and keep the path between the TPS254900-Q1 device and the dc-dc converter short to help minimize voltage drops.
Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input voltage in conjunction with input power-bus inductance and input capacitance when the IN pin is in the high-impedance state (before turnon). Theoretically, the peak voltage is 2 times the applied voltage. The second cause is due to the abrupt reduction of output short-circuit current when the TPS254900-Q1 device turns off and energy stored in the input inductance drives the input voltage high. Applications with large input inductance (for example, a connection between the evaluation board and the bench power supply through long cables) may require large input capacitance to prevent the voltage overshoot from exceeding the absolute-maximum voltage of the device.
During the short-to-battery (EN = HIGH) condition, the input voltage follows the output voltage until OVP protection is triggered (t(OV_OUT)). After the TPS254900-Q1 device responds and turns off the power switch, the stored energy in the input inductance can cause ringing.
Based on the three situations described, 10-µF and 0.1-µF low-ESR ceramic capacitors, placed close to the input, are recommended.
Consider the following application situations when choosing the output capacitors.
After an output short occurs, the TPS254900-Q1 device abruptly reduces the OUT current, and the energy stored in the output power-bus inductance causes voltage undershoot and potentially reverse voltage as it discharges.
Applications with large output inductance (such as from a cable) benefit from the use of a high-value output capacitor to control the voltage undershoot.
For USB port applications, because the VBUS pin is exposed to IEC61000-4-2 level-4 ESD, use a low-ESR capacitance to protect OUT.
The TPS254900-Q1 device is capable of handling up to 18-V battery voltage. When VBUS is shorted to the battery, the LCR tank circuit formed can induce ringing. The peak voltage seen on the OUT pin depends on the short-circuit cable length. The parasitic inductance and resistance varies with length, causing the damping factor and peak voltage to differ. Longer cables with larger resistance reduce the peak current and peak voltage. Consider high-voltage derating for the ceramic capacitor, because the peak voltage can be higher than twice the battery voltage.
Based on the three situations described, a 10-µF, 35-V, X7R, 1210 low-ESR ceramic capacitor placed close to OUT is recommended. If the battery voltage is 16 V and a 16-V transient voltage suppressor (TVS) is used, then the capacitor voltage can be reduced to 25 V. Considering temperature variation, placing an additional 35-V aluminum electrolytic capacitor can lower the peak voltage and make the system more robust.
The capacitance on the BIAS pin helps the IEC ESD performance on the DM_IN and DP_IN pins.
When a short to battery on DP_IN, DM_IN and/or OUT occurs, high voltage can be seen on the BIAS pin. Place a 2.2-µF, 50-V, X7R, 0805, low-ESR ceramic capacitor close to the BIAS pin. The whole current path from BIAS to GND should be as short as possible. Additionally, use a 5.1-kΩ discharge resistor from BIAS to OUT.
The TPS254900-Q1 device can withstand high transient voltages due to LCR tank ringing, but in order to make OUT, DP_IN, and DM_IN robust, place one TVS close to the OUT pin, and another TVS close to the BIAS pin. When choosing the TVS, the reverse standoff voltage VR depends on the battery voltage (16 V or 18 V). Considering the peak pulse power capability, a 400-W device is recommended such as an SMAJ16 for a 16-V battery or an SMAJ18 for an 18-V battery.
VBAT = 14 V | t = 10 µs/div |
VBAT = 18 V | t = 10 µs/div |
t = 10 µs/div |
t = 10 µs/div |
t = 10 µs/div |
RBIAS = 5.1 kΩ | t = 2 µs/div |
t = 10 µs/div |
t = 10 µs/div |
RBIAS = 5.1 kΩ | t = 2 µs/div |
R(BIAS) = 5.1 kΩ | t = 2 µs/div | R(DP_OUT) = 15 kΩ |
The TPS254900-Q1 device is designed for a supply voltage range of 4.5 V ≤ VIN ≤ 6.5 V, with its power switch used for protecting the upstream power supply when a fault such as overcurrent or short to ground occurs on the USB port. Therefore, the power supply should be rated higher than the current-limit setting to avoid voltage drops during overcurrent or short-circuit conditions.
Layout best practices for the TPS254900-Q1 are listed as follows.
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High Speed USB Platform Design Guidelines, Intel
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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