SLVSD03 December   2015 TPS2559-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Thermal Sense
      2. 9.3.2 Overcurrent Protection
      3. 9.3.3 FAULT Response
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation with VIN Undervoltage Lockout (UVLO) Control
      2. 9.4.2 Operation with EN Control
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Step by Step Design Procedure
        2. 10.2.2.2 Input and Output Capacitance
        3. 10.2.2.3 Programming the Current-Limit Threshold
        4. 10.2.2.4 Design Above a Minimum Current Limit
        5. 10.2.2.5 Design Below a Maximum Current Limit
        6. 10.2.2.6 Accounting for Resistor Tolerance
        7. 10.2.2.7 Power Dissipation and Junction Temperature
        8. 10.2.2.8 Auto-Retry
        9. 10.2.2.9 Two-level Current-limit
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRC|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

  • Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a low-inductance trace.
  • Placing a high-value electrolytic capacitor and a 100-nF bypass capacitor on the output pin is recommended when large transient currents are expected on the output.
  • The traces routing the RILIM resistor to the device should be as short as possible to reduce parasitic effects on the current limit accuracy.
  • The PowerPAD should be directly connected to PCB ground plane using wide and short copper trace.

12.2 Layout Example

TPS2559-Q1 layout_slvscl54.gif Figure 31. TPS2559-Q1 Board Layout