SLVSEZ5A July   2020  – December 2020 TPS25814

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Recommended Capacitance
    5. 6.5  Thermal Information
    6. 6.6  Power Supply Characteristics
    7. 6.7  Power Consumption
    8. 6.8  PP_5V Power Switch Characteristics
    9. 6.9  Power Path Supervisory
    10. 6.10 CC Cable Detection Parameters
    11. 6.11 CC VCONN Parameters
    12. 6.12 Thermal Shutdown Characteristics
    13. 6.13 Input/Output (I/O) Characteristics
    14. 6.14 BC1.2 Characteristics
    15. 6.15 I2C Requirements and Characteristics
    16. 6.16 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Paths
        1. 8.3.1.1 Internal Sourcing Power Paths
          1. 8.3.1.1.1 PP_5V Current Clamping
          2. 8.3.1.1.2 PP_5V Local Overtemperature Shut Down (OTSD)
          3. 8.3.1.1.3 PP_5V OVP
          4. 8.3.1.1.4 PP_5V UVLO
          5. 8.3.1.1.5 PP_5Vx Reverse Current Protection
          6. 8.3.1.1.6 PP_CABLE Current Clamp
          7. 8.3.1.1.7 PP_CABLE Local Overtemperature Shut Down (OTSD)
          8. 8.3.1.1.8 PP_CABLE UVLO
      2. 8.3.2 Cable Plug and Orientation Detection
        1. 8.3.2.1 Configured as a Source
      3. 8.3.3 Overvoltage Protection (CC1, CC2)
      4. 8.3.4 Default Behavior Configuration (ADCIN1, ADCIN2)
      5. 8.3.5 BC 1.2 (USB_P, USB_N)
      6. 8.3.6 Digital Interfaces
        1. 8.3.6.1 Fault Indicators ( FAULT )
        2. 8.3.6.2 Sink Attachment Indicator ( SINK )
        3. 8.3.6.3 Polarity Indicator ( POL )
        4. 8.3.6.4 Power Management ( CHG_HI)
        5. 8.3.6.5 Battery Charging Control (CTL)
        6. 8.3.6.6 Debug Accessory Detection ( DEBUG)
        7. 8.3.6.7 Disable the Port (EN)
        8. 8.3.6.8 I2C Interface
      7. 8.3.7 I2C Interface
        1. 8.3.7.1 I2C Interface Description
        2. 8.3.7.2 I2C Clock Stretching
        3. 8.3.7.3 I2C Address Setting
        4. 8.3.7.4 Unique Address Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Strapping to Configure Default Behavior
      2. 8.4.2 Power States
      3. 8.4.3 Schottky for Current Surge Protection
      4. 8.4.4 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Type C DFP Port Implementation with Embedded Controller
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Type-C Connector VBUS Capacitors
          2. 9.2.1.1.2 VBUS Schottky and TVS Diodes
          3. 9.2.1.1.3 VBUS Snubber Circuit
        2. 9.2.1.2 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V Power
      1. 10.1.1 VIN_3V3 Input Switch
    2. 10.2 1.5-V Power
    3. 10.3 Recommended Supply Load Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Top TPS25814 Placement and Bottom Component Placement and Layout
    2. 11.2 Layout Example
    3. 11.3 Component Placement
    4. 11.4 Routing and View Placement
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-C80E3968-6D2A-4C6F-A368-0371D5D02ECB-low.gif Figure 5-1 RSM Package32-pin QFNTop View
Table 5-1 Pin Functions
PIN TYPE(1) RESET Description
NAME NO.
ADCIN1 2 I Hi-Z Configuration input. Connect to a resistor divider to LDO_3V3.
ADCIN2 3 I Hi-Z Configuration input. Connect to a resistor divider to LDO_3V3.
CC1 24 I/O Hi-Z I/O for USB Type-C .
CC2 25 I/O Hi-Z I/O for USB Type-C .
CHG_HI 17 I Hi-Z Charge logic input to select between minimum or maximum Type-C current advertisement.
CTL 30 I Hi-Z This pin controls which BC 1.2 mode is used. Pull to GND for CDP mode. Pull high for DCP mode.
DEBUG 6 O Hi-Z Open-drain logic output that is asserted low when a Type-C debug accessory is detected.
EN 5 I Low When this pin is pulled low or left floating, the device will be disabled and remain in the Type-C Error Recovery state.
FAULT 7 O Hi-Z Open-drain logic output that asserts when an over-current fault is detected.
GND 11,12,14,15,16,19,20 — — Ground. Connect to ground plane.
I2C_EC_SCL 9 I Hi-Z I2C slave serial clock input. Tie to pullup voltage through a resistor when used or unused. Connect to Embedded Controller (EC).
I2C_EC_SDA 8 I/O Hi-Z I2C slave serial data. Open-drain output. Tie to pullup voltage through a resistor when used or unused. Connect to Embedded Controller (EC).
I2C_EC_IRQ 10 O Hi-Z I2C slave interrupt. Active low. Connect to external voltage through a pull-up resistor. May also be used as a general purpose digital output. Connect to Embedded Controller (EC).
LDO_1V5 4 O — Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This pin cannot source current to external circuits.
LDO_3V3 1 O — Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with capacitance CLDO_3V3 to GND.
POL 13 O Hi-Z Open-drain logic output that gives the information needed to mux the superspeed lines. It is asserted low when CC2 is connected to the cable CC line.
PP5V 28,29 I — 5-V System Supply to VBUS, supply for CCy pins as VCONN.
SINK 18 O Hi-Z Open-drain logic output that asserts low when a Type-C Sink is identified on the CC lines.
USB_N 23 I/O Hi-Z I/O for BC 1.2 functionality. Connect to the USB D- line.
USB_P 22 I/O Hi-Z I/O for BC 1.2 functionality. Connect to the USB D+ line.
VBUS 26,27 I/O 5-V to 20-V input. Bypass with capacitance CVBUS to GND.
VIN_3V3 32 I — Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
NC 21,31 — — This pin has no functionality. Leave floating.
(1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output