SLVSE94G September   2018  – June 2024 TPS2663

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Hot Plug-In and Inrush Current Control
        1. 8.3.1.1 Thermal Regulation Loop
      2. 8.3.2  PGOOD and PGTH
        1. 8.3.2.1 PGTH as VOUT Sensing Input
      3. 8.3.3  Undervoltage Lockout (UVLO)
      4. 8.3.4  Overvoltage Protection (OVP)
      5. 8.3.5  Input Reverse Polarity Protection (B_GATE, DRV)
      6. 8.3.6  Reverse Current Protection
      7. 8.3.7  Overload and Short-Circuit Protection
        1. 8.3.7.1 Overload Protection
          1. 8.3.7.1.1 Active Current Limiting at 1 × IOL (TPS26630 and TPS26632 Only)
          2. 8.3.7.1.2 Active Current Limiting With 2 × IOL Pulse Current Support (TPS26631, TPS26633, TPS26635, TPS26636, and TPS26637 Only)
        2. 8.3.7.2 Short-Circuit Protection
          1. 8.3.7.2.1 Start-Up With Short Circuit on Output
      8. 8.3.8  Output Power Limiting, PLIM (TPS26632, TPS26633, TPS26635, TPS26636, and TPS26637 Only)
      9. 8.3.9  Current Monitoring Output (IMON)
      10. 8.3.10 FAULT Response (FLT)
      11. 8.3.11 IN_SYS, IN, OUT, and GND Pins
      12. 8.3.12 Thermal Shutdown
      13. 8.3.13 Low Current Shutdown Control (SHDN)
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Power Path Protection in a PLC System
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Current-Limit Threshold—R(ILIM) Selection
        2. 9.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 9.2.2.3 Output Buffer Capacitor – COUT
        4. 9.2.2.4 PGTH Set Point
        5. 9.2.2.5 Setting Output Voltage Ramp Time—(tdVdT)
          1. 9.2.2.5.1 Support Component Selections— RPGOOD and C(IN)
        6. 9.2.2.6 Selecting Q1, Q2 and TVS Clamp for Surge Protection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Simple 24-V Power Supply Path Protection
      2. 9.3.2 Priority Power MUX Operation
      3. 9.3.3 Input Protection for a Compact 24-V Auxiliary Power Supply for Servo Drives
    4. 9.4 Dos and Do Nots
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Transient Protection
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
  • PWP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

–40°C ≤ TA = TJ ≤ +125°C, 4.5 V < V(IN_SYS) = V(IN) < 60 V, V(SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
UVLO INPUT (UVLO)
UVLO_ton(dly) UVLO switch turnon delay UVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV with V(PGTH  < V(PGTHF), C(dVdT) ≥ 10 nF,  [C(dVdT) in nF] 742 + 49.5 x C(dVdT) µs
UVLO_ton(fast_dly) UVLO switch turnon delay (fast) UVLO↑  (100 mV above V(UVLOR)) to FET ON with V(PGTH) > V(PGTHF) 70 150 251 µs
UVLO_toff(dly) UVLO switch turnoff delay UVLO↓(20 mV below V(UVLOF)) to FLT↓ 9 11 16 µs
tUVLO_FLTdly) UVLO to fault de-assertion delay UVLO↑  to FLT ↑ delay 500 617 700 µs
OVER VOLTAGE PROTECTION INPUT (OVP)
OVP_tOFF(dly) OVP switch turnoff delay OVP↑ (20 mV above V(OVPR)) to FLT↓ 8.5 11 14 µs
OVP_ton(fast_dly) OVP switch turnon delay (fast) OVP↓ (100 mV below V(OVPF)) to FET ON with V(PGTH ) > V(PGTHF) 58 129 225 µs
OVP_ton(dly) OVP switch disable delay OVP↓ (100 mV below V(OVPF)) to FET ON with V(PGTH ) < V(PGTHF), C(dVdT) ≥ 10 nF,  [C(dVdT) in nF] 150 + 49.5 x C(dVdT) µs
tOVC(dly) Maximum duration in over voltage clamp operation TPS26632, TPS26633,TPS26635 and TPS26636 Only 162 ms
OVC_tFLT(dly) FLT assertion delay in over voltage clamp operation TPS26632, TPS26633,TPS26635 and TPS26636 Only 617 µs
SHUTDOWN CONTROL INPUT (SHDN)
tSD(dly) SHUTDOWN entry delay SHDN↓ (below V(SHUTF)) to FET OFF 0.8 1 1.5 µs
CURRENT LIMIT
tFASTTRIP(dly) Hot-short response time I(OUT) > I(SCP) 1 µs
Soft short response I(FASTTRIP) < I(OUT) < I(SCP) 2.2 3.2 4.5 µs
tCL_PLIM(dly) Maximum duration in current & (power limiting: TPS26632, TPS26633, TPS26635, TPS26636 and TPS26637) 129 162 202 ms
tCB(dly) Maximum duration in 2x current limiting  I(OL) < I(OUT) ≤ I(2xOL) 20 25.5 31 ms
tCBRetry(dly) Retry delay in Pulse over current limiting MODE = GND, TPS26631, TPS26633,TPS26635 and TPS26636 Only 550 670 800 ms
tCL_PLIM_FLT(dly) FLT delay in current & (power limiting: TPS26632, TPS26633, TPS26635, TPS26636 and TPS26637) 1.09 1.3 1.6 ms
REVERSE CURRENT BLOCKING (RCB) COMPARATOR
tRCB(fast_dly) Reverse protection comparator dectection delay (reverse) (V(IN_SYS) – V(OUT))↓ (1 V overdrive below V(REVTH)) to V(DRV) – V(IN_SYS) = V(DRV_OH) 0.17 0.37 µs
tRCB(dly) (V(IN_SYS) – V(OUT))↓ (10 mV overdrive below V(REVTH)) to V(DRV) – V(IN_SYS) = V(DRV_OH) 0.48 3 µs
tRCB(flt_dly) Fault assertion Delay (V(IN_SYS) – V(OUT))↓ (10 mV overdrive below V(REVTH)) to FLT↓ 500 617 800 µs
tFWD_FLT(dly) Reverse protection comparator dectection delay (forward) (V(IN_SYS) – V(OUT))↑ (10 mV overdrive above V(FWDTH)) to V(BGATE) – V(IN_SYS) = 5 V, C(BFET-IN_SYS) = 4.7 nF 0.87 ms
Fault de-assertion Delay (V(IN_SYS) – V(OUT))↑ (10 mV overdrive above V(FWDTH)) to FLT↑ 434 605 800 µs
OUTPUT RAMP CONTROL (dVdT)
t(FASTCHARGE) Output ramp time in fast charging C(dVdT) = Open, 10% to 90% V(OUT), C(OUT) = 1 µF; V(IN) = 24V 350 495 700 µs
t(dVdT) Output ramp time C(dVdT) = 22 nF, 10% to 90% V(OUT), V(IN) = 24V 8.35 ms
POWER GOOD (PGOOD)
tPGOODR PGOOD delay (deglitch) time Rising edge 1.07 1.3 1.6 ms
tPGOODF PGOOD delay (deglitch) time Falling edge, PGTH↓ (10mV below V(PGTHF)) 1.3 2.12 4 µs
FAULT FLAG (FLT)
tCB_FLT(dly) FLT assertion delay in Pulse over current limiting Delay from I(OUT) > I(OL) to FLT↓. TPS26631, TPS26633, TPS26635 and TPS26636 Only 22 25.5 30 ms
THERMAL PROTECTION
t(TSD_retry) Retry delay in TSD MODE = GND 500 648 800 ms
t(Treg_timeout) Thermal Regulation Timeout 2.3 2.54 2.9 s