SLVSH67 September   2024 TPS26750

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
      1. 5.1.1 TPS26750 - Absolute Maximum Ratings
      2. 5.1.2 TPS26750 - Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
      1. 5.3.1 TPS26750 - Recommended Operating Conditions
    4. 5.4  Recommended Capacitance
    5. 5.5  Thermal Information
      1. 5.5.1 TPS26750 - Thermal Information
    6. 5.6  Power Supply Characteristics
    7. 5.7  Power Consumption
    8. 5.8  PP_5V Power Switch Characteristics
    9. 5.9  POWER_PATH_EN Characteristics - TPS26750
    10. 5.10 Power Path Supervisory
    11. 5.11 CC Cable Detection Parameters
    12. 5.12 CC VCONN Parameters
    13. 5.13 CC PHY Parameters
    14. 5.14 Thermal Shutdown Characteristics
    15. 5.15 ADC Characteristics
    16. 5.16 Input/Output (I/O) Characteristics
    17. 5.17 BC1.2 Characteristics
    18. 5.18 I2C Requirements and Characteristics
    19. 5.19 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  USB-PD Physical Layer
        1. 7.3.1.1 USB-PD Encoding and Signaling
        2. 7.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 7.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 7.3.1.4 USB-PD BMC Transmitter
        5. 7.3.1.5 USB-PD BMC Receiver
        6. 7.3.1.6 Squelch Receiver
      2. 7.3.2  Power Management
        1. 7.3.2.1 Power-On And Supervisory Functions
        2. 7.3.2.2 VBUS LDO
      3. 7.3.3  Power Paths
        1. 7.3.3.1 Internal Sourcing Power Paths
          1. 7.3.3.1.1 PP_5V Current Clamping
          2. 7.3.3.1.2 PP_5V Local Overtemperature Shut Down (OTSD)
          3. 7.3.3.1.3 PP_5V OVP
          4. 7.3.3.1.4 PP_5V UVLO
          5. 7.3.3.1.5 PP_5Vx Reverse Current Protection
          6. 7.3.3.1.6 PP_CABLE Current Clamp
          7. 7.3.3.1.7 PP_CABLE Local Overtemperature Shut Down (OTSD)
          8. 7.3.3.1.8 PP_CABLE UVLO
      4. 7.3.4  Cable Plug and Orientation Detection
        1. 7.3.4.1 Configured as a Source
        2. 7.3.4.2 Configured as a Sink
        3. 7.3.4.3 Configured as a DRP
        4. 7.3.4.4 Dead Battery Advertisement
      5. 7.3.5  Overvoltage Protection (CC1, CC2)
      6. 7.3.6  Default Behavior Configuration (ADCIN1, ADCIN2)
      7. 7.3.7  ADC
      8. 7.3.8  BC 1.2 (USB_P, USB_N)
      9. 7.3.9  Digital Interfaces
        1. 7.3.9.1 General GPIO
        2. 7.3.9.2 I2C Interface
      10. 7.3.10 Digital Core
      11. 7.3.11 I2C Interface
        1. 7.3.11.1 I2C Interface Description
          1. 7.3.11.1.1 I2C Clock Stretching
          2. 7.3.11.1.2 I2C Address Setting
          3. 7.3.11.1.3 Unique Address Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Strapping to Configure Default Behavior
      2. 7.4.2 Power States
    5. 7.5 Thermal Shutdown
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Programmable Power Supply (PPS) - Design Requirements
        2. 8.2.1.2 Liquid Detection Design Requirements
        3. 8.2.1.3 BC1.2 Application Design Requirements
        4. 8.2.1.4 USB Data Support Design Requirements
        5. 8.2.1.5 EPR Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programmable Power Supply (PPS)
        2. 8.2.2.2 Liquid Detection
        3. 8.2.2.3 BC1.2 Application
        4. 8.2.2.4 USB Data Support
        5. 8.2.2.5 Power Delivery EPR Support
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Programmable Power Supply (PPS) Application Curves
        2. 8.2.3.2 Liquid Detection Application Curves
        3. 8.2.3.3 BC1.2 Application Curves
        4. 8.2.3.4 USB Data Support Application Curves
        5. 8.2.3.5 EPR Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 3.3V Power
        1. 8.3.1.1 VIN_3V3 Input Switch
      2. 8.3.2 1.5V Power
      3. 8.3.3 Recommended Supply Load Capacitance
    4. 8.4 Layout
      1. 8.4.1 TPS26750 - Layout
        1. 8.4.1.1 Layout Guidelines
          1. 8.4.1.1.1 Recommended Via Size
          2. 8.4.1.1.2 Minimum Trace Widths
        2. 8.4.1.2 Layout Example
          1. 8.4.1.2.1 TPS26750 Schematic Layout Example
          2. 8.4.1.2.2 TPS26750 Layout Example - PCB Plots
            1. 8.4.1.2.2.1 TPS26750 Component Placement
            2. 8.4.1.2.2.2 TPS26750 PP5V
            3. 8.4.1.2.2.3 TPS26750 PP_EXT
            4. 8.4.1.2.2.4 TPS26750 VBUS
            5. 8.4.1.2.2.5 TPS26750 I/O
            6. 8.4.1.2.2.6 TPS26750 PPEXT Gate Driver
            7. 8.4.1.2.2.7 TPS26750 GND
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RSM|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.4.1.2.2.2 TPS26750 PP5V
The 10uF decoupling capacitor (C8) need to be placed as close as possible to the PP5V pins of TPS26750. DO NOT use traces for PP5V. The PP5V power plane needs to be sized to support up to 3.6A (up to 3A for sourcing, 600mA for Vconn). When connecting the PP5V pins (pins 28 and 29) to the 5V power plane, use a minimum of 4 vias in parallel and close to the device to improve current sharing. Minimize the bottle necks cause by other vias or traces, large bottle necks reduces the efficiency of the power plane. The bulk capacitors (C6, C7, and C9) represent capacitances from the system 5V rail, these are placed further away from TPS26750 on the same PP5V power plane. Refer to figure 10-21 and figure 10-22 for placement and trace reference.