SLVSBR5C December   2012  – June  2015 TPS27082L

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dissipation Ratings
    7. 6.7 Typical Characteristics
      1. 6.7.1 PFET Q1 Minimum Safe Operating Area (SOA)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 ON/OFF
      2. 7.4.2 Fastest Output Rise Time
      3. 7.4.3 Controlled Output Rise Time
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Configuring Q1 ON-Resistance
        2. 8.2.2.2 Configuring Turnon Slew Rate
        3. 8.2.2.3 Configuring Turnoff Delay
        4. 8.2.2.4 OFF Isolation Under VIN Transients
        5. 8.2.2.5 Low Voltage ON/OFF Interface
        6. 8.2.2.6 On-Chip Power Dissipation
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 TFT LCD Module Inrush Current Control
      2. 8.3.2 Standby Power Isolation
      3. 8.3.3 Boost Regulator With True Shutdown
      4. 8.3.4 Single Module Multiple Power Supply Sequencing
      5. 8.3.5 Multiple Modules Interdependent Power Supply Sequencing
      6. 8.3.6 Multiple Modules Interdependent Supply Sequencing Without a GPIO Input
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Improving Package Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

  • VIN and VOUT traces should be as short and wide as possible to accommodate for high current.
  • The VIN pin should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 1-μF ceramic with X5R or X7R dielectric. This capacitor should be placed as close to the device pins as possible.
  • The VOUT pin should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is one-tenth of the VIN bypass capacitor of X5R or X7R dielectric rating. This capacitor should be placed as close to the device pins as possible.

10.2 Layout Example

TPS27082L tps27082l.gifFigure 23. Layout Diagram

10.3 Thermal Considerations

For higher reliability it is recommended to limit TPS27082L IC’s die junction temperature to less than 125°C. The IC junction temperature is directly proportional to the on-chip power dissipation. Use the following equation to calculate maximum on-chip power dissipation to restrict the die junction temperature target to safe limits:

Equation 6. TPS27082L Eq6_pdmax_lvsbr5.gif

where

  • TJ(MAX) is the target maximum junction temperature,
  • TA is the operating ambient temperature,
  • and RθJA is the package junction to ambient thermal resistance.

10.3.1 Improving Package Thermal Performance

The package RθJA value under standard conditions on a High-K board is available in Dissipation Ratings. RθJA value depends upon the PCB layout. An external heat sink and/or a cooling mechanism like a cold air fan can help reduce RθJA and thus improving device thermal capability. Refer to TI’s design support web page at www.ti.com/thermal for a general guidance on improving device thermal performance.