TPS281C30E has an enchanced EFT immunity compared to the other variants. The E variant implemented a stronger gate pulldown circuit which helps the device in the OFF state to stay OFF when an EFT pulses comes in. Due to the active circuit in the OFF state, the E variant will draw a higher current from the supply during the OFF state I_Q(OFF)compared to the other variants. E version device will have Hi-Z on the output while OFF, with leakage current I_OUT(OFF).

The max EFT voltage level V_(EFT) will largely depending on the components used in the test circuit. The larger the output capacitor, and the smaller the coupling capacitor, the higher the EFT voltage level can be tolerated. As the coupling capacitor value is fixed in most EFT standards, increasing the output capacitor value can be an effecitive way to increase the maximum EFT voltage level.

Figure 8-21 shows the setup for EFT testing. TPS281C30E is tested to pass +/- 2.5 kV EFT at VS and VOUT with 10nF output capacitor and 100pF coupling capacitor as shown in the diagram. The output capacitor can be increased if passing higher level of EFT is desired. The A, B, C, D variants are tested to pass +/- 2 kV EFT at VS and VOUT with 22nF output capacitor and 100pF coupling capacitor. The DIAG_EN has to be high for A, B, C, D version in the OFF state in order to not enter the sleep state and have the EFT immunity stated above, while the DIAG_EN can be either high or low for E version as the EFT protection circuit is always active. The test conditions are outlined in EFT Test Conditions.

There is a strong pulldown circuitry to keep the power FET OFF during OFF state EFT transient. The circuitry is activated after EFT_DELAY period to not affect the normal turn-off slew rate. However, the part is not protected during the EFT_DELAY period as illustrated in Figure 8-22.

Figure 8-21 EFT Test Setup

Figure 8-22 EFT Timing Diagram