When an inductive load is switching off, the output voltage is pulled down to negative, due to the inductance characteristics. The power FET may break down if the voltage is not clamped during the current-decay period. To protect the power FET in this situation, internally clamp the drain-to-source voltage, namely V_DS,clamp, the clamp diode between the drain and gate. Please note that the internal V_DS,clamp will only be available in version A, B. For version C, D, E, an external clamp across VDS or at VOUT is required to dissipate the inductive energy properly.

During the current-decay period (T_DECAY), the power FET is turned on for inductance-energy dissipation. Both the energy of the power supply (E_S) and the load (E_LOAD) are dissipated on the high-side power switch itself, which is called E_HSD. If resistance is in series with inductance, some of the load energy is dissipated in the resistance.

From the high-side power switch’s view, E_HSD equals the integration value during the current-decay period.

Equation 5.

Equation 6.

Equation 7.

When R approximately equals 0, E_HSD can be given simply as:

Equation 8.

Figure 8-11 Driving Inductive Load

Figure 8-12 Inductive-Load Switching-Off Diagram

As discussed previously, when switching off, battery energy and load energy are dissipated on the high-side power switch, which leads to the large thermal variation. For each high-side power switch, the upper limit of the maximum safe power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation condition. TI provides the upper limit of single-pulse energy that devices can tolerate under the test condition: V_S = 24 V, inductance from 0.1 mH to 400 mH, R = 0 Ω, FR4 2s2p board, 2× 70-μm copper, 2× 35-μm copper, thermal pad copper area 600 mm².