SLUSAR9D December   2011  – December 2021 TPS28225-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO)
      2. 7.3.2 Output Active Low
      3. 7.3.3 Enable/Power Good
      4. 7.3.4 3-State Input
      5. 7.3.5 Bootstrap Diode
      6. 7.3.6 Upper and Lower Gate Drivers
      7. 7.3.7 Dead-Time Control
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching the MOSFETs
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.3 Application Curves

Example is the same for the TPS28225-Q1. The efficiency in this example was achieved using TPS28225 driver with 8-V drive at different switching frequencies as in Figure 8-4 is shown in Figure 8-8, Figure 8-9, Figure 8-10, Figure 8-11, and Figure 8-12.

GUID-984EB4F4-0A8C-459B-9D40-D94CD90C21C7-low.gifFigure 8-8 Efficiency vs Load Current
GUID-78DFE52D-73BB-404E-A035-51414CD7299D-low.gifFigure 8-10 Efficiency vs Load Current
GUID-B46582F8-5C34-418F-A744-457016D229D4-low.gifFigure 8-12 Efficiency vs Load Current
GUID-2FEFE2E9-2FA7-4CC1-8E24-D19874064431-low.gifFigure 8-9 Efficiency vs Load Current
GUID-B9A874D7-6D36-46DF-A59C-3B5BB5859FB8-low.gifFigure 8-11 Efficiency vs Load Current

When using the same power stage in Figure 8-4, the driver with the optimal drive voltage and optimal dead time can boost efficiency up to 5%. The optimal 8-V drive voltage versus 5-V drive contributes 2% to 3% efficiency increase and the remaining 1% to 2% can be attributed to the reduced dead time. The 7-V to 8-V drive voltage is optimal for operation at switching frequency range above 400 kHz and can be illustrated by observing typical RDS(on) curves of modern FETs as a function of their gate drive voltage. This is shown in Figure 8-13.

GUID-DFC69453-27E2-4806-816E-178206BB8192-low.gif
On-Resistance Variation with Gate-to-Source Voltage
Figure 8-13 RDS(on) of MOSFET as Function of VGS
GUID-72C0E7FF-00B9-4A73-8D1F-7906FD922B81-low.gifFigure 8-14 Drive Power as Function of VGS and FSW

Figure 8-13 and Figure 8-14 show that the RDS(on) at 5-V drive is substantially larger than at 7 V and above that the RDS(on) curve is almost flat. This means that moving from 5-V drive to an 8-V drive boosts the efficiency because of lower RDS(on) of the MOSFETs at 8 V. Further increase of drive voltage from 8 V to 12 V only slightly decreases the conduction losses but the power dissipated inside the driver increases dramatically (by 125%). The power dissipated by the driver with 5-V, 8-V, and 12-V drive as a function of switching frequency from 400 kHz to 800 kHz. It should be noted that the 12-V driver exceeds the maximum dissipated power allowed for an SOIC-8 package even at 400-kHz switching frequency.