This section discusses the implementation of the low current mode with a low quiescent current (Iq) feature in HCS-family devices.

Functionality

To supply ECUs that provide monitoring functions while the car is in the park mode (key-off mode), a low power mode (LPM) of operation is designed where the device consumes very low quiescent current even while the outputs are ON. The capabilities of the device are:

• Low quiescent current of the order of 10 uA from the battery input while delivering 100s of mAs of current with a maximum current of 800 mA per channel (limited only by wake threshold setting).
• Protection against short circuit at the output while in low power mode. In other words, if a short circuit were to occur with the output ON in low power mode, the device protects itself.
• Automatically respond to load current increase by transitioning to the ACTIVE state. The device provides a wake signal to the microcontroller (that is in sleep mode) to wake the system up through the  FLT /WAKE_SIG pin.

Figure 8-11 LPM Functional Block Diagram

Entry to and Exit from LPM

The device can be transitioned to the LPM state by writing to the LPM register. Any or both of the FETs can be ON in LPM, the set of channels to be ON is set by SW_STATE register (so needs to be written to before the write to the LPM register) and the command to go to LPM is received. Once in LPM the output state cannot be changed unless moved to ACTIVE state. The other requirement is that the switches that are enabled before the LPM mode bit is set, has to complete the inrush current phase before the transition to LPM is completed. All of the configuration registers are retained while the device is in the LPM state.

Please note that there is no output ON-to-OFF or OFF-to-ON tranistion possible during the ACTIVE to LPM transition. Only the channels that are already ON in ACTIVE state are allowed to be ON in LPM mode. The STATE has to be set to be ON in ACTIVE state and the channel must be fully ON before the LPM transition begins. Similarly, if the channel is OFF in the in LPM mode, that channel can be turned ON only in the ACTIVE state (after the transition to ACTIVE state is complete)

Figure 8-12 LPM Entry and Exit

Exiting from LPM

1. When the VDD supply is lost or the supply voltagae falls belows the POR threshold – the device transitions to OFF or SLEEP state where all register config is lost. The entry back to ACTIVE state is per the normal power up sequence including a wake signal from the MCU.
2. Special SPI command to write “0” to the LPM bit.
3. Current increase beyond the threshold set in the range from 200 mA to 800 mA using SPI configuration register LPM using register .

System Wake

The MCU or controller can write a special command to the LPM register setting the LPM bit to 0 to set the ICs in LPM state back to the ACTIVE state. When the digital core wakes up, the device interprets the command to go the ACTIVE state (if the special command is received). If the received command is not the SPI write to the LPM register, then the device stays in the LPM state. After the device is in the ACTIVE state – the MCU has to read to clear LPM bit to pull the  FLT pin back up and clear any residual LPM condition.

Automatic Wake on Load Current Increase

The device takes the responsibility to wake the system and itself up when there is a load current increase beyond the programmed threshold. The threshold current (either ECU load current demand increase or an output short circuit) to activate the switch to the main MOSFET is in the range of 200 mA to 800 mA (programmable). The expectation is that the maximum current draw from the ECU while in low quiescent current mode (without the need to wake up) is lower than the programmed threshold. The additional load current demand and the transition to the active state is signaled to the MCU or the System Basis Chip (SBC) with a falling edge of the  FLT or  WAKE_SIG (active low pull-up resistor to VDD) that can be used as an interrupt by the MCU or the SBC to wake up the system. The device can then be polled over SPI to see if the  FLT or  WAKE_SIG pin transition was caused by the load ECU current demand or a short circuit. The device is in the ACTIVE state with full SPI diagnostic capability and the short circuit fault condition can be read back from the fault register. The device registers a FAULT and as over-current protection fault only if the overcurrent is confirmed in the ACTIVE state. After the device transitions to ACTIVE because of a load current increase, the LPM bit in the LPM register remains set to 1. To go to LPM state again, the LPM bit in the LPM register needs to be set to 0 and then 1 again.

The timing diagram of the device response to a load current increase to any of the output channels is shown in .

Figure 8-13 LPM to ACTIVE State Transition on Load Current Increase

In the case of a slow increase in load current, the device detects a load current in excess of the programmed threshold for ACTIVE state transition. The channel output transitions smoothly to the low Ron FET state and achieve full load current capability with only a minor drop in the output voltage. However, in the case where the load current increases fast so that a second higher protection current threshold is reached before the FET is fully ON, the device switches off the channel. This is done to protect against potential short circuit at the output. The device then turns back on the channel in ACTIVE state and with the main FET ON. The output is then fully protected against a short and the channel either provides the full load current or stays in the overcurrent protection mode.