SLVSGY2 October   2023 TPS2HCS10-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Mechanisms
        1. 8.3.1.1 Programmable Fuse Protection
        2. 8.3.1.2 Thermal Shutdown
        3. 8.3.1.3 Overcurrent Protection And Capacitive Load Charging
        4. 8.3.1.4 Reverse Battery
      2. 8.3.2 Diagnostic Mechanisms
        1. 8.3.2.1 VOUT Short-to-Battery and Open-Load
          1. 8.3.2.1.1 Detection With Channel Output (FET) Enabled
          2. 8.3.2.1.2 Detection With Channel Output Disabled
        2. 8.3.2.2 Digital Current Sense Output
          1. 8.3.2.2.1 RSNS Value and Accuracy / Resolution of Current Measurement
            1. 8.3.2.2.1.1 High Accuracy Load Current Sense
            2. 8.3.2.2.1.2 SNS Output Filter
        3. 8.3.2.3 Output Voltage and FET Temperature Sensing
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 SLEEP
      3. 8.4.3 CONFIG/ACTIVE
      4. 8.4.4 Battery Supply Input (VBB) Under-voltage
      5. 8.4.5 LOW POWER MODE (LPM) State
      6. 8.4.6 LIMP HOME state
      7. 8.4.7 SPI Mode Operation
    5. 8.5 TPS2HC10S Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Thermal Considerations
        2. 9.2.2.2 Configuring the Capacitive Charging Mode
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.3.2.1.2 Detection With Channel Output Disabled

While the channel output is disabled (FET is off), and if the OL_OFF_EN_CHx bit in the DIAG_CONFIG_CHx register (CH1 shown as example) is set high, an internal comparator will detect the condition of VOUT. The detection circuit is shown in Figure 8-7. If the load is disconnected (open load condition) or there is a short to battery the VOUT voltage will be higher than the open load threshold (VOL,off) and a fault is indicated on the FLT pin unless masked in the FAULT_MASK register. The faulted channel can be determined by reading the FLT_STAT_CHx (CH1 shown as example) register with the OL_OFF_CHx bit set if there is a open load on that channel. An internal pull-up current source of programmable value (through configuration bits OL_PU_STR in the DIAG_CONFIG_CHx register) is used, so no external component is required if an open load must be detected even with some on-board load and there is significant leakage or other current draw even when the load is disconnected. A pull-up resistor and switch can be added externally to set the VOUT voltage above the VOL,off during open load conditions, if the internal pull-up is not sufficient.

GUID-20230323-SS0I-52NN-HMSL-XV7ZV2CXXCGL-low.svg
This figure assumes that the device ground and the load ground are at the same potential. In a real system, there may be a ground shift voltage of the order of 1 V.
Figure 8-7 Short to Battery and Open Load Detection

While the switch is disabled and OL_OFF_EN_CHx bit in the DIAG_CONFIG_CHx is set high, the fault indication mechanism will continuously represent the present status. For example, if VOUT decreases from greater than VOL to less than VOL, the fault indication is reset.

Further, to distinguish between an open load and short-to-battery condition, a second diagnostic can be enabled (in the off-state) by setting the SVBB_EN_CHx bit in the DIAG_CONFIG_CHx register (after the device detect either an open load or short-to-battery). The device then enables a pulldown on the output. If the short-to-battery condition exists, VOUT voltage will remain higher than the open load threshold (VOL,off) the the SHRT_VBB_CHx bit will be set high.