SLVSGY2 October   2023 TPS2HCS10-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Mechanisms
        1. 8.3.1.1 Programmable Fuse Protection
        2. 8.3.1.2 Thermal Shutdown
        3. 8.3.1.3 Overcurrent Protection And Capacitive Load Charging
        4. 8.3.1.4 Reverse Battery
      2. 8.3.2 Diagnostic Mechanisms
        1. 8.3.2.1 VOUT Short-to-Battery and Open-Load
          1. 8.3.2.1.1 Detection With Channel Output (FET) Enabled
          2. 8.3.2.1.2 Detection With Channel Output Disabled
        2. 8.3.2.2 Digital Current Sense Output
          1. 8.3.2.2.1 RSNS Value and Accuracy / Resolution of Current Measurement
            1. 8.3.2.2.1.1 High Accuracy Load Current Sense
            2. 8.3.2.2.1.2 SNS Output Filter
        3. 8.3.2.3 Output Voltage and FET Temperature Sensing
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 SLEEP
      3. 8.4.3 CONFIG/ACTIVE
      4. 8.4.4 Battery Supply Input (VBB) Under-voltage
      5. 8.4.5 LOW POWER MODE (LPM) State
      6. 8.4.6 LIMP HOME state
      7. 8.4.7 SPI Mode Operation
    5. 8.5 TPS2HC10S Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Thermal Considerations
        2. 9.2.2.2 Configuring the Capacitive Charging Mode
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.7 SPI Mode Operation

The TPS2HCS10-Q1 communicates with the host controller through a high-speed SPI serial interface. The interface has three logic inputs: clock (CLK), chip select ( CS), serial data in (SDI), and one data out (SDO). The SDO is tri-stated when the CS pin is high. The maximum SPI clock rate is 10MHz, but is limited in practice by the series protection resistor.

The device supports simple daisy chain SPI. This mode can be used with or without CRC.

The communication between the TPSHCS10 IC and the controller or MCU is through a SPI bus in a primary-secondary configuration. The external MCU is always an SPI primary device that sends command requests on the SDI pin of the TPS2HCS10-Q1 IC and receives device responses on the SDO pin of the IC. The TPS2HCS10-Q1 device is always an SPI secondary (or slave) device that receives command requests over the SDI line and sends responses (such as status and measured values) to the external MCU over the SDO line.

The TPS2HCS10-Q1 device can be connected to the primary MCU in the following formats:

GUID-20230925-SS0I-JCNK-7V0L-0TMD5DPPPCKS-low.svgFigure 8-14 Independent Secondary Configuration (Separate nCS Signal)
GUID-20230925-SS0I-JBB5-JJJB-9XHKWG9MSLVB-low.svgFigure 8-15 Daisy Chain Configuration

SPI interface

The SPI interface pin behavior is described in this section

Chip Select ( CS or nCS)

The system microcontroller selects the TPS2HCS10-Q1 to receive communication using the  CS pin. With the  CS pin in a logic LOW state, command/configuration words may be sent to the TPS2HCS10-Q1 via the serial input (SDI) pin, and the device information can be retrieved by the microcontroller via the serial output (SDO) pin. The falling edge of the  CS enables the SDO output and latches the content of the CH_FLT_TYPE/FAULT_GLOBAL_TYPE register that will be sending out on SDO. The microcontroller may issue a READ command to retrieve information stored in the registers. Rising edge on the  CS pin initiate following actions:

  1. Addressed registers are updated if there is no SPI communication error and if it is an SPI write command.
  2. Read clear register is cleared if a READ command to this register was issued during CS = LOW.

To avoid any corrupted data, it is essential the HIGH-to-LOW and LOW-to-HIGH transitions of the  CS signal occur only when SCLK is in a logic LOW state. A clean  CS signal is needed to ensure no incomplete SPI words are sent to the device. This pin is internally pulled up to the VDD rail.

System Clock

The system clock (SCLK) pin clocks the internal shift register of the TPS2HCS10-Q1. The SDI data is latched into the input shift register on the falling edge of the SCLK signal. The SDO pin shifts the device stored information out on the rising edge of SCLK. The SDO data is available for the microcontroller to read on the falling edge of SCLK.

False clocking of the shift register must be avoided to ensure validity of data and it is essential the SCLK pin be in a logic LOW state whenever  CS pin makes any transition. Therefore, it is recommended that the SCLK pin gets pulled to a logic LOW state as long as the device is not accessed and the  CS pin is at a logic HIGH state. When the  CS is in a logic HIGH state, any signal on the SCLK and SDI pins will be ignored and the SDO pin remains as a high impedance output.

Serial Data In (SDI) and Serial Data Out (SDO)

The SDI pin is used for serial instruction data input. SDI information is latched into the input shift register on the falling edge of the SCLK when  CS is low.

The SDO pin is the output from the internal shift register. This pin is internally pulled up to the VDD rail. SDO pin is HiZ when the  CS pin is high. Each successive rising SCLK edge makes the next data bit available for the microcontroller to read on the falling edge of SCLK. SDO will go back to high-impedance when  CS is high. FLT

CRC Error Detection and Checking of clocks

Setting the CRC_EN bit high enables CRC error detection. A CRC-4-ITU-Normal Check Sequence (FCS) is then sent along with each serial transaction. The 4-bit CRC is based on the normal generator polynomial X4+X+1 with CRC starting value = 1111. When CRC is enabled, the TPS2HCS10-Q1 expects a check byte appended to the SDI program/configure data that it receives.

To program a complete word, exact bits of information (shown in following table) must be enter into the device. When CRC is disabled, the IC enables register write only if exactly bits have been clocked in. When CRC is enabled, the IC enables register write only if exactly bits have been clocked in with no CRC errors. In case the word length exceeds or does not meet the required length or there is CRC errors, the SPI_ERR bit in the CH_FLT_TYPE_FAULT_GLOBAL_TYPE is asserted to logic “1”,and the data received is considered invalid. Note the SPI_ERR bit is not flagged if SCLK is not present. The SPI_ERR will be sent back to SPI Main device on SDO during next chip access. Note that clear on read applies only when there is no SPI error when the register is read.

SPI Frame Format

The device uses a 24-bit frame width (when CRC is not used) with the format as shown in Figure 8-16. Please note that the 16-bit wide "Data Out" in the SDO output is always for the previous SPI command frame (Read or Write).

GUID-20230323-SS0I-D4JL-TSVL-SP4SZKBKS4SZ-low.svgFigure 8-16 24-bit Read or Write, CRC_EN=0