SNVSCN9A September   2024  – December 2024 TPS3423 , TPS3424

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Inputs
        1. 7.3.1.1 Push-Button Input (PB)
        2. 7.3.1.2 Push-Button Timing Programmability
        3. 7.3.1.3 KILL
      2. 7.3.2 Outputs
        1. 7.3.2.1 Interrupt (INT)
        2. 7.3.2.2 RESET / RESET
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Power Button Control with TPS3424
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 PB and RESET Topology
          2. 8.2.1.2.2 Short Press Time (tSP) and Long Press Time (tLP) selection
          3. 8.2.1.2.3 Interrupt and Kill Feature
        3. 8.2.1.3 Application Curve
      2. 8.2.2 High Voltage Connection
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

TPS3423 TPS3424 Pin Configuration Option: TPS3423 DRL Package 8-Pin SOT-5X3 Top View Figure 5-1 Pin Configuration Option: TPS3423
DRL Package
8-Pin SOT-5X3
Top View
TPS3423 TPS3424 Pin Configuration Option TPS3423 DRL Package 6-Pin SOT-5X3 Top ViewFigure 5-2 Pin Configuration Option TPS3423
DRL Package
6-Pin SOT-5X3
Top View
TPS3423 TPS3424 Pin Configuration Option TPS3424 DRL Package 8-Pin SOT-5X3 Top View Figure 5-3 Pin Configuration Option TPS3424
DRL Package
8-Pin SOT-5X3
Top View
TPS3423 TPS3424 Pin Configuration Option TPS3424 DRL Package 6-Pin SOT-5X3 Top ViewFigure 5-4 Pin Configuration Option TPS3424
DRL Package
6-Pin SOT-5X3
Top View
Table 5-1 TPS3423 - Pin Functions
TPS3423 I/O DESCRIPTION
PIN NAME 8 PIN SOT-5X3 6 PIN SOT-5X3
PB1 1 1 I Push-button input 1, refer Section 7.3.1.1 for additional details.
GND 2 2 - Ground connection for IC.
VDD 3 3 I Supply connection, connect a 0.1µF capacitor near the pin for best performance.
INT2 4 O Interrupt output for push-button input 2, INT2 is open drain active low output which toggles from every short press and long press on push-button input 2 as described in Section 7.3.2.1
INT1 5 O Interrupt output for push-button input 1, INT1 is open drain active low output which toggles from every short press and long press on push-button input 1 as described in Section 7.3.2.1
RESET1/RESET1 6 4 O RESET output for push-button input 1. The response of RESET to short press and long press is described in Section 7.3.2.2.
RESET2/RESET2 7 5 O RESET output for push-button input 2. The response of RESET to short press and long press is described in Section 7.3.2.2.
PB2 8 6 I Push-button input 2, refer Section 7.3.1.1 for additional details.
Table 5-2 TPS3424 - Pin Functions
TPS3424 I/O DESCRIPTION
PIN NAME 8 PIN SOT-5X3 6 PIN SOT-5X3
PB 1 1 I Push-button input, refer Section 7.3.1.1 for additional details.
GND 2 2 - Ground connection for IC.
VDD 3 3 I Supply connection, connect a 0.1µF capacitor near the pin for best performance.
SPT 4 Connect capacitor to program short press time as described in Section 7.3.1.1 for SPT Cap version.
LPT 5 O Connect capacitor to program long press time as described in Section 7.3.1.1 for LPT Cap version.
RESET/RESET 6 4 O RESET output for the device. The response of RESET to short press and long press is described in Section 7.3.2.2.
INT 7 5 O Interrupt output. INT is open drain active low output which toggles from every short press and long press on push-button input as described in Section 7.3.2.1
KILL 8 6 I Kill is feedback from the host. RESET can be de-asserted in the latched version by pulling KILL low. Connect this pin to VDD if not used. Please refer Section 7.3.1.3 for additional details.