SNVSCN9 September   2024 TPS3423 , TPS3424

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD ratings (Industrial)
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Inputs
        1. 7.3.1.1 Push-Button Input (PB)
        2. 7.3.1.2 Push-Button Timing Programmability
        3. 7.3.1.3 KILL
      2. 7.3.2 Outputs
        1. 7.3.2.1 Interrupt (INT)
        2. 7.3.2.2 RESET / RESET
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Power Button Control with TPS3424
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 High Voltage Connection
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD Supply pin voltage 1 6 V
VPB Push-button pin input voltage 0 VDD V
VKILL KILL pin Voltage  0 VDD V
VINT Interrupt pin voltage 0 VDD V
VRESET Output pin voltage 0 VDD V
IRESET Output pin current 0 5 mA
TA Ambient temperature (free-air temperature) -40 125 ℃
CSPT SPT capacitor (1) 125 nF
CLPT LPT capacitor 125 nF
(1) SPT capacitor value must be less than LPT capacitor