SLVS165N April   1998  – July 2022 TPS3820 , TPS3823 , TPS3824 , TPS3825 , TPS3828

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics for TPS3823A-33 only
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Manual Reset (MR)
      2. 8.3.2 Active-High or Active-Low Output
      3. 8.3.3 Push-Pull or Open-Drain Output
      4. 8.3.4 Watchdog Timer (WDI)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Supply Rail Monitoring With Watchdog Time-Out and 200-ms Delay
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Decoupling WDI During Reset Event
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Spice Models
      2. 12.1.2 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.8 Switching Characteristics

At RL = 1 MΩ, CL = 50 pF, and TJ = 25°C, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ttout Watchdog time out TPS3820 VDD ≥ VIT− + 0.2 V
See Figure 7-1 		112 200 300 ms
TPS3823/4/8, TPS3823A 0.9 1.6 2.5 s
td Delay time TPS3820 VDD ≥ VIT− + 0.2 V
See Figure 7-1 		15 25 37 ms
TPS3823/4/5/8, TPS3823A 120 200 300
tPHL Propagation (delay) time,
high-to-low-level output		 MR to RESET delay
(TPS3820/3/5/8, TPS3823A) 		VDD ≥ VIT− + 0.2 V,
VIL = 0.3 × VDD,
VIH = 0.7 × VDD 		0.1 µs
VDD to RESET delay VIL = VIT– – 0.2 V,
VIH = VIT– + 0.2 V		 25
tPLH Propagation (delay) time,
low-to-high-level output		 MR to RESET delay (TPS3824/5) VDD ≥ VIT− + 0.2 V,
VIL = 0.3 × VDD,
VIH = 0.7 × VDD 		0.1 µs
VDD to RESET delay (TPS3824/5) VIL = VIT– – 0.2 V,
VIH = VIT– + 0.2 V		 25
GUID-6EB1D47B-3D7B-4D62-AC2E-499396E00729-low.gif Figure 7-1 Timing Diagram