SNVSC50 june   2023 TPS389006

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I2C
      2. 8.3.2 Auto Mask (AMSK)
      3. 8.3.3 PEC
      4. 8.3.4 VDD
      5. 8.3.5 MON
      6. 8.3.6 NIRQ
      7. 8.3.7 ADC
      8. 8.3.8 Time Stamp
    4. 8.4 Device Functional Modes
      1. 8.4.1 Built-In Self Test and Configuration Load
        1. 8.4.1.1 Notes on BIST Execution
      2. 8.4.2 TPS389006 Power ON
      3. 8.4.3 General Monitoring
        1. 8.4.3.1 IDLE Monitoring
        2. 8.4.3.2 ACTIVE Monitoring
        3. 8.4.3.3 Sequence Monitoring 1
          1. 8.4.3.3.1 ACT Transitions 0→1
          2. 8.4.3.3.2 SLEEP Transition 1→0
          3. 8.4.3.3.3 SLEEP Transition 0→1
        4. 8.4.3.4 Sequence Monitoring 2
          1. 8.4.3.4.1 ACT Transition 1→0
    5. 8.5 Register Maps
      1. 8.5.1 BANK0 Registers
      2. 8.5.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.7 ADC

The ADC used in the TPS389006 runs on a 1Mhz clock with an effective sampling rate of 1/8 MHz (= 125 kHz). Initially, the ADC records with a resolution of 12 bits (1LSB = 0.41667mV) which is later round off to 8-bit data for I2C transaction. (1LSB = 5mV) The ADC uses ping-pong architecture in which it requires 2us for both sampling and conversion per channel with a total of 2 sampling channels. While CH0 performs coarse conversion, CH1 does fine conversion and vice versa.

Digitized 8-bit data is updated once the fine conversion is completed, which occurs once every 8 μs. Each I2C transaction initiated for reading 8-bit MON_LVL data (the ADC data of a particular channel), 8-bit data is paused from updating until the I2C transaction completes.

Voltage scaling is done using a resistor ladder, but for differential mode channels, a chopping circuit is used to get the average of both of the voltages (VMON + VMON_RS)/2 since VMON_RS can be negative and can’t be converted into an ADC code. VMON – VMON_RS is calculated digitally by subtracting ((VMON + VMON_RS) /2) from VMON and then multiplying by 2.

The MONX channels can be configured in 1x (0.2V to 1.475V) or 4x mode (0.8V to 5.5V). For differential mode channels configured in 1x mode, (MON1 and MON2) the ADC range is limited up to 1.7V. To configure an ADC channel above 1.7 V, please use 4x mode.

Real time voltage measurements use Equation 2.

Equation 1. Vlvl = ((ADC[7:0] * 5mV) + 0.2) * (VRANGE_MULT)
  1. ADC[7:0] is translated to a corresponding decimal value. The value of ADC[7:0] corresponding to MON1-MON6 can be read from registers 0x40-0x45 of Section 8.5.1.
  2. VRANGE_MULT corresponds to the selected monitor voltage multiplier set in register 0x1F of Section 8.5.2.
  3. VRANGE_MULT is set to a decimal 1 or 4 value depending on monitored value.